[SI-LIST] Re: plane cutouts under ac-coupling cap pads
- From: hassan@xxxxxxxx
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>, Matthew Severini <MSeverini@xxxxxxxxxxxx>
- Date: Thu, 11 Jul 2013 06:40:25 -0400
literally forcing only differential mode propagation along the two
caps. You should be able to see that discontinuity in your HFSS
simulations. Look at the single-ended return loss.
If you optimized your plane cutouts based on single-ended
s-parameter performance, then you'll also have problems in
differential mode performance. You should use differential mode
s-parameter performance to optimize the cutouts.
For plane cutout optimization in HFSS, it's sufficient to replace
the caps with shorts since you're only finding a solution to the
impedance discontinuity created by the capacitor pads that are wider
than the traces connected to the caps.
Best regards,
Hassan.
On Wed 07/10/13 7:04 PM , Matthew Severini MSeverini@xxxxxxxxxxxx
sent:
I guess the clock is running as well. I should also say though, when
I simulated, I simulated all of the pcie lanes signaling at once. In
the simulation I also included the entire board with the air
dielectric boundaries, so any resonances that may be occurring in
that cavity have been taken into account in the simulation. With all
of that, I am still seeing much improved performance in the
simulation, that is not being realized in hardware.
Matt Severini
Signal Integrity Engineer
mseverini@xxxxxxxxxxxx [1]
(801) 987-7127
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx
[2]] On Behalf Of Matthew Severini
Sent: Wednesday, July 10, 2013 5:56 PM
To: si-list@xxxxxxxxxxxxx [3]
Subject: [SI-LIST] Re: plane cutouts under ac-coupling cap pads
First off thank you for your rapid response. The signals are routed
as micro strip. Obviously the ground plane underneath them is the one
that is cutout. Below this ground plane is the top of a gssg
structure. So, in other words underneath the cutouts there are two
signal layers before the next ground. We were careful to keep all
signals on those planes as far away from the cutouts as possible. I
could see how this would create coupling, and extra noise, but I am
fairly certain that the way I am measuring the eye (IBERT in a Xilinx
fpga, and sig test over pcie to the fpga), the lane I am testing is
the only lane on the entire board with anything going on, besides the
power rails, which we are well isolated from.
Matt Severini
Signal Integrity Engineer
mseverini@xxxxxxxxxxxx [4]
(801) 987-7127
-----Original Message-----
From: Vinu Arumugham [vinu@xxxxxxxxx [5]]
Sent: Wednesday, July 10, 2013 5:37 PM
To: Matthew Severini
Subject: Re: [SI-LIST] plane cutouts under ac-coupling cap pads
If in simulation/measurement you are looking at only one diff pair,
then it is possible that the cutouts have inadvertently increased
coupling which will make the actual signal look worse.
Is the first layer below the cutout a solid ground plane? A
description of the layers on which the signal is routed would be
useful.
Thanks,
Vinu
On 07/10/2013 04:25 PM, Matthew Severini wrote:
> I have, the common mode performance is more or less unchanged. I
should say also, because we only have a single ended tdr, that
measurement was done single ended on each leg of the pair.
>
> Matt Severini
>
> Signal Integrity Engineer
> mseverini@xxxxxxxxxxxx [6]
> (801) 987-7127
>
>
>
>
>
> -----Original Message-----
> From: Vinu Arumugham [vinu@xxxxxxxxx [7]]
> Sent: Wednesday, July 10, 2013 5:18 PM
> To: Matthew Severini
> Subject: Re: [SI-LIST] plane cutouts under ac-coupling cap pads
>
> Have you looked at both common mode and differential mode
performance?
>
> Thanks,
> Vinu
>
> On 07/10/2013 04:10 PM, Matthew Severini wrote:
>> Content-Type: text/plain; charset="us-ascii"
>> Content-Transfer-Encoding: quoted-printable Hello experts,
>>
>> I have a problem that has me totally stumped, so I thought you
may
>> have som= e ideas. We have some signal lanes with dc-blocking
caps, that run at about=
>> 10ghz. I noticed that the planes had not been cutout
underneath
>> the pads o= f these caps, which has obvious issues. I simulated
the
>> cap structure in HF= SS to find an optimum cutout size, and
rolled it
>> into the next spin of the = board. All of my simulations claim
that
>> the new structure should have a hug= e positive influence on the
si
>> of these lanes. Unfortunately, when we measu= re the eye, it
seems to be about the same, or ever so slightly worse! I did=
>> a tdr on the cards with and without the cutout, and the
cutouts definitely=
>> seem to flatten the impedance curve along the trace. I haven't
>> been able t= o do a vna measurement yet because I cannot access
one side of the trace. I=
>> have ordered boards with only those caps on them so that I can
>> make this m= easurement, but all the initial data seems to say
that
>> the transmission mea= surements will also be better with the
cutouts.
>> I was wondering if anyone h= ad some possible explanations as to
why the eye would be a little worse, in=
>> almost every measurement (according to sig test), when the
>> impedance is fl= atter.
>>
>> Thanks for your help,
>>
>> Matt Severini
>>
>> Signal Integrity Engineer
>> mseverini@xxxxxxxxxxxx
>> (801) 987-7127
>>
>>
>> [signature_image]
>>
>>
>> This e-mail (and any attachments) is confidential and may be
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not
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and
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