[SI-LIST] Re: placement of decoupling caps (again)
- From: "Victor Snesarev" <vsnesarev@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 15 Apr 2004 06:33:32 -0400
Paul Mobbs wrote:
"I think another interesting experiment would be to use the recommended
amount of decoupling and then start taking it away until you see a
problem.
I wonder what those results would look like and under what circumstances
the
results would be the most dramatic."
Altera has an app note on hish-speed PCB design for FPGAs and they
describe an experiment like this.
http://www.altera.com/literature/an/an315.pdf
They inject noise onto the power plane and measure jitter on a 40"
trace. Page 67 summarizes their results:
"Because of board problems, the jitter reading numbers in Table 7 are
generally high. However, the jitter-reading comparison is still very
important. Testing shows that when the decoupling capacitors are
removed, the performance initially improves, but then worsens."
The app note contains other recommendations on decoupling capacitor
placement that seem to contradict some of the things stated in this
thread.
Victor
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Paul Mobbs
Sent: Wednesday, April 14, 2004 7:33 PM
To: Raymond.Anderson@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: placement of decoupling caps (again)
I read a bit of the paper posted and it looks like it compares "global"
decoupling (spread all over) to "local" decoupling (right near the pin).
Although there is a lot of reference to "lumped" capacitance, it doesn't
look like they stuck it all in one place in their tests.
I think another interesting experiment would be to use the recommended
amount of decoupling and then start taking it away until you see a
problem.
I wonder what those results would look like and under what circumstances
the
results would be the most dramatic.
BTW Is there anything that can be done to eliminate all those "Out of
office" replies when I post?
Regards,
Paul Mobbs
Mobbs Engineering
Email: paul@xxxxxxxxxxxxx
Voice: (415) 563-1454
----- Original Message -----
From: "Ray Anderson" <Raymond.Anderson@xxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, April 14, 2004 4:19 PM
Subject: [SI-LIST] Re: placement of decoupling caps (again)
> Lee Ritchey wrote:
> > UMR did a paper in 1995 that determined location is not important as
long
> > as you don't cut up the power planes. Others have repeated those
same
> > tests, as have I, and come up with the same answers.
> >
> > The proponents of location matters need to do some testing to show
that
> > their position is valid.
> >
> > Lee
> >
> > Lee W. Ritchey
> > Speeding Edge
> > P. O. Box 2194
> > Glen Ellen, CA 95442
> > Phone- 707-568-3983
> > FAX- 707-568-3504
> >
>
> OK, how about a thought experiment.
>
> Scenario one:
> --------------
>
> You've got a rather large PCB (say 24" x 24") with no cuts in the
power
> planes. The board has a fast, current hungry chip (say 400 MHz clock
> rate, 80psec rise time, 50 amps of transient current) in one corner
> clocking away. Some number of appropriate decaps are located within an
> inch of the chip. Everything works OK (whatever that means...).
>
> Scenario two:
> -------------
>
> You've got a rather large PCB (say 24" x 24") with no cuts in the
power
> planes. The board has the same fast, current hungry chip in one corner
> clocking away. The same decaps as were used in scenario one are now
> located at the opposite corner of the board (about 34 inches away).
Does
> everything still work OK?
>
>
> Without actually doing the experiment, I'll go out on a limb and
venture
> to say no. Granted, this is an extreme contrived example, but I really
> don't think you can make a blanket statement and say that the location
> of the decoupling capacitors on a PCB is a "don't care" decision.
>
>
> -Ray Anderson
> Sun Microsystems Inc.
>
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