Dear all There are a lot of good discussion on the placement of decoupling capacitors. I agree with Raymond that the "rule of experts" is not always right. When and where will affect the result. For ADSL, the decoupling below 3MHz is critical. For SDRAM of 50MHz, the decoupling from 10MHz to 400MHz is critical. In power integrity, there are several stage. VRM=>PCB=>Package=>Die. The final is at the power ground pin of Die. At PCB level, it could not be completely solved. Whether the decoupling is good or bad should be decided by the impedance at the power ground pin of Die and the noise source of Die. Therefore, I think it is of no use to discuss which is better or not without the details of the product. My recommandation is that "Do simulation and check the impedance". Best Regards Zhangkun 2004.4.16 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu