[SI-LIST] Re: placement of decoupling caps (again)

  • From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
  • To: Raymond.Anderson@xxxxxxx
  • Date: Fri, 16 Apr 2004 13:16:55 +0800

Dear all

There are a lot of good discussion on the placement of decoupling capacitors. I 
agree with Raymond that the "rule of experts" is not always right. When and 
where will affect the result. For ADSL, the decoupling below 3MHz is critical. 
For SDRAM of 50MHz, the decoupling from 10MHz to 400MHz is critical.

In power integrity, there are several stage.


The final is at the power ground pin of Die. At PCB level, it could not be 
completely solved. Whether the decoupling is good or bad should be decided by 
the impedance at the power ground pin of Die and the noise source of Die.

Therefore, I think it is of no use to discuss which is better or not without 
the details of the product.

My recommandation is that "Do simulation and check the impedance".

Best Regards


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