[SI-LIST] Re: pattern generator code for PCI express simulation
- From: kalevi@xxxxxxxxxx
- To: "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Tue, 24 Apr 2012 04:05:27 -0700 (PDT)
You can use encode=DW8B10B in the LFSR statement to make your bit sequence
8b10b.
________________________________
From: Joel Brown <joel@xxxxxxxxxx>
To: SI-List <si-list@xxxxxxxxxxxxx>
Sent: Monday, April 23, 2012 8:04 PM
Subject: [SI-LIST] pattern generator code for PCI express simulation
Wondering what people use for generating stimulus for PCI Express channel
simulation.
My understanding is that it takes millions of bits of data to generate a
worse case eye diagram.
I have been using the following:
LFSR(0 1V 1n 5ps 5ps 'data_rate' 1 [7,4,1] rout=0)
Which I think came with an example file for one of my models.
Since it is only 7 bits the pseudo random pattern will be at most 127 bits
long and it is not 8b10b encoded.
So my thoughts are to use a much longer sequence and run it through an
8b10b encoder.
I found Verilog code to do this but now I have to figure out how to
incorporate it into an Hspice simulation.
Thanks - Joel
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