[SI-LIST] Re: packaging guidelines for diff-pairs
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Bond, David" <David.Bond@xxxxxxx>
- Date: Tue, 31 May 2011 09:17:57 -0700
Bypass on the back of the PCB is a compromise of practicality. It can
work for supplies that have an adequate checkerboard under the thermal
slug, and where the PCB isn't too thick. Outside the center thermal
slug, "Drill baby drill!" makes a nice sound bite for politicians, but
mostly headaches for PCB designs. If you are targeting many layer
boards, those will be thick boards, and the Z axis partial via
inductance for any given via pair will be massive. Noted power
integrity specialist Nancy Reagan recommends: "Just say no."
Steve.
On 5/31/2011 8:54 AM, Bond, David wrote:
> Hi Experts.
> We're having a debate about the optimal ball map for a 3-2-3 flip-chip
> BGA with respect to the optimal placement of the differential pairs and
> the powers/grounds that surround them. Ultimately, simulation will
> verify/validate the package design. My goal here is to get as good a
> starting point as possible to minimize the design-simulate-analyze loop
> as much as possible...
>
>
>
> Here's the details
>
> 1. Baud rate of 11Gbaud
>
> 2. Many differential pairs each running at 11G
>
> 3. Medium sized package ~30mmx30mm, 1mm ball pitch, full array
>
> 4. SerDes uses two supplies VDD1 and VDD2, where VDD2 is a higher
> voltage than VDD1
>
> a. Diff-pair outputs are driven primarily by Vdd1, but VDD2 is
> used for additional drive
>
> b. Diff-pair inputs are referenced to ground
>
> 5. Core supply, VDD, is separate from VDD1 and VDD2
>
> 6. Grounds are separate on the silicon, but tied together in the
> package
>
> 7. As a component vendor, we don't have access to details on the
> link partner's package design and can only recommend PCB layouts to our
> customers
>
> 8. The expected PCB will be many layers>>8, may have access to
> back-drill, blind/buried vias. Transmit and receive pairs are run on
> separate layers separated by either vdd or gnd. We recommend that both
> have a gnd reference - of course there's no guarantee what the customer
> will actually do on the PCB.
>
> 9. The package substrate uses these layers to run the diff pairs:
>
> a. Top layer for RX pairs
>
> b. Gnd
>
> c. TX pairs via directly from the bump on the silicon to this
> layer
>
> d. VDD1
>
> e. Other layers are used for other supplies, thru which the tx/rx
> pairs and vdd1 and vdd2 must via to get to the package balls
>
> 10. Current draw and di/dt on VDD1 is 2x that of VDD2
>
>
>
> Here are the questions:
>
> 1. The core supply, vdd, is a checkerboard the size of the die.
> Bypass caps will be placed on the backside of the board directly between
> the vdd/gnd vias. Is there any benefit to extending the checkerboard
> beyond the size of the die? I contend that we need to get the vdd1/vdd2
> supplies of the SerDes as close to the edge of the die and pushing they
> out to accommodate 2 or 3 more rings of the vdd/gnd checkerboard only
> serves to increase their impedance and hence the noise the SerDes sees.
>
>
>
> 2. The SerDes vendor advises that the inputs are referenced to
> ground, but the outputs are referenced to vdd1 and gnd. So, they advise
> that the input diff-pairs be surrounded by grounds, while the outputs be
> surrounded by vdd1 and gnd. This seems odd to me. Consider the case
> where our part is used on both ends of the link. If the outputs are
> referenced to vdd1 on the transmitting part, they're connected to inputs
> which are referenced to gnd on the receiver. At the receiving end, the
> inputs run on the top layer of the package substrate and have no vdd1
> reference. That will force the return path to change layers thru either
> inter-plane capacitance or bypass caps which just doesn't seem optimal.
> If DC blocking caps are used, then the diff pair must be brought to the
> surface of the board which will force the return path to move to the
> plane directly beneath the cap which could introduce yet another
> discontinuity in the reference plane.
>
>
>
>
>
> 3. Wouldn't the optimal package design strive to do this:
>
> a. Bring the VDD1 and VDD2 balls in as close as possible to the
> edge of the die where the SerDes is located, AND
>
> b. Use a VDD1/VDD2 and gnd checkerboard in the ballmpa with
> bypassing on the back of the PCB
>
> c. Tie the ground planes of the package to which both the TX and
> RX pairs are referenced to the PCB's ground plane was well as possible
> (especially where the TX and RX pairs are transitioning thru the package
> substrate and PCB), AND
>
> d. Advise our customers' to reference their tracks to ground?
>
> Of course, we don't know what the link partner component may do, but I
> doubt that they would leave their inputs and outputs without any ground
> reference because it would be difficult to meet the RL, IL and
> conversion specifications which are typical for these types of high
> speed interfaces. Any advice here?
>
>
>
> 4. Is there a good source for package design for these types of
> designs? Ideally with example layouts of differential pairs
>
>
>
>
> David Bond
>
> (who has a new-found admiration for those who can concisely ask
> questions :-) )
>
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
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