[SI-LIST] Re: package SSN model accuracy requirements

  • From: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • To: gary_pratt@xxxxxxxxxxx
  • Date: Mon, 14 Mar 2005 15:06:47 -0500

Gary
I have a few questions about AMS solutions that I have not yet seen 
discussed.

I understand that it is theoretically possible to model anything in an 
AMS language.  However, at this point in time, I have not seen a 
soup-to-nuts comparison of an HSPICE model of a complex differential 
equalized driver or receiver and an AMS equivalent model, as either a 
simulator correlation or ultimately a measurement correlation.  As a 
user at many different levels I would like to see performance 
benchmarks, model development time benchmarks, and relative and absolute 
accuracy comparisions with both simulation and measurement.  All 
apples-to-apples comparions.

I have heard many accolades regarding AMS languages over the last few 
years, and do not doubt that it may be possible to eventually convince 
silicon vendors to switch over to AMS as the preferred modeling 
language, but there are many practical issues that I have not yet seen 
dealt with, including:

    * Switchover costs associated with changing a silicon vendor's
      in-house overall device modeling process to AMS from HSPICE or
      other internal Spice.  

    * A workable general process for converting Hspice or other Spice
      model into an AMS equivalent as a transition strategy from Spice
      to AMS.
          o This would require a method to encapsulate the entire I/O
            buffer in and AMS language,  from
                + core predrivers to final output stages, inclusive of
                  pre-emphasis, de-emphasis,
                + driver PVT control circuitry,
                + differential balance circuitry,
                + FIR filtering at the driver and/or receiver,
                + driver/receiver out-of-band signaling and control
                  circuitry, etc ....
          o Tradeoffs for speed vs. accuracy in the translation

    * Performance comparisons between the converted AMS model and the
      original Spice model.
          o Performance comparisons should be on the same computational
            platform.

    * Accuracy and speed comparions of translated AMS models vs. Spice
      and native AMS I/O buffer models.
          o Accuracy to simulated and measured data should be shown.


Gary, are there any documents from you, your company, or the industry in 
general that discuss these issues at length?

I would agree that the Mentor IBIS/Eldo/AMS simulation platform has the 
potential for some valuable contributions and performance advantages to 
modeling and simulation methodology for board, package and chip-level 
design.  However, to my knowledge, there is no substantive data that 
shows that these advantages have been achieved and correlated to real 
measured systems with the kind of accuracy which Chris Cheng, Steve 
Weir, myself and others are accustomed to.  If you have real information 
to the contrary, I would love to see it.

Ultimately, as both a user and a model developer, correlation to 
measured results is king.  Show me the simulation and measurements side 
by side on a real device in a real system, and I'll be a believer.  
First show me the correlated results of one high-performance link.  Then 
show me the correlated results for all links in the systems switching, 
including all package effects including ground and power bounce (Which 
implies that the simulation must be capable of fully floating power and 
ground networks from device to device.)

best regards,

scott



Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Pratt, Gary wrote:

>Great question Todd.  The answer is that the top three SI tool vendors
>all have VHDL-AMS and Verilog-AMS simulators in-house.  All that is
>required is sufficient industry pressure to encourage them to port the
>simulators to their SI tools. And, I've heard there is another SI vendor
>almost ready to burst onto the market with their AMS solution.
>
>Also, I know of at least one inexpensive VHDL-AMS simulator on the
>market which an SI vendor could possibly OEM (and I suspect there are
>more).  I also know there is at least one vendor who has a VHDL-AMS
>parser that outputs C code which can then be used to drive any simulator
>which accepts C modules. =20
>
>I suspect once a tool vendor were motivated to search, there would be
>other solutions out there waiting to be found as well.
>
>Somehow, it seems industry is always able to meet market demand.  I'm
>sure AMS will be no exception. =20
>
>Gary
>
> =20
>
>-----Original Message-----
>From: Todd Westerhoff (twesterh) [mailto:twesterh@xxxxxxxxx]=20
>Sent: Monday, March 14, 2005 8:27 AM
>To: michael.mirmak@xxxxxxxxx; weirsi@xxxxxxxxxx; Pratt, Gary;
>Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: package SSN model accuracy requirements
>
>Okay, I'll probably get flamed for asking this, but it's worth the risk
>anyway:
>
>When we talk about AMS, it seems to me we're really talking about two
>things in practice - VHDL-AMS and Verilog-AMS.
>
>If a vendor walked in today and plunked down a CD with VHDL-AMS model on
>it, my guess is that they would have developed it with Mentor tools.
>I'd also guess that they wouldn't have tested it with the Cadence
>toolset, nor have plans to.
>
>I think the converse is also true - a Verilog-AMS model was likely
>developed with Cadence tools and not tested with their Mentor
>counterparts.
>
>I don't know which vendors support AMS beyond Cadence and Mentor.  There
>certainly could be others, I'm just not aware of them.
>
>So - my question (you knew it would come along eventually, right?)
>
>In current practice, doesn't AMS end up essentially being a
>vendor-specific solution?  I fully understand that this is a new
>technology and that my question isn't "fair" from a long term point of
>view.  But - as others have said - we get measured on what we do today
>to deliver product in the near term.  Simulation technologies that hold
>promise two years out are fine, but they have little immediate impact.
>
>I'm just wondering if I'm right with my current impressions about
>Verilog-AMS and VHDL-AMS being vendor-specific in practice.  If that
>really is the case, then I'm also wondering how we propose to get from
>where we are now to a point where we have models that are portable
>across tools again.
>
>Todd. =20
>
>
>Todd Westerhoff
>High Speed Design Group Manager
>Cisco Systems
>1414 Massachusetts Ave - Boxboro, MA - 01719 email:twesterh@xxxxxxxxx
>ph: 978-936-2149
>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>
>"Always do right.
> This will gratify some people and astonish the rest."
>
>- Mark Twain
>
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