[SI-LIST] Re: options for reducing EMI

  • From: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • To: <sherman.chen@xxxxxxx>
  • Date: Wed, 3 Sep 2014 09:30:54 -0400

Chen
You can certainly do that, but it's a band aid for whatever the actual
problem is.  You should just not be radiating at 8 GHz.

Regards,

Scott


Scott McMorrow
Teraspeed® Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com


On Wed, Sep 3, 2014 at 9:20 AM, Chen, Sherman <sherman.chen@xxxxxxx> wrote:

> Thanks, Steve.
> The freq. exceeding the EMI margin is 8GHz. Enabling SSC should help on
> that I think.
> Any impact & precaution for turning SSC on? Looks there would be no big
> issue since all our chip vendors claims their products work fairly well
> with SSC on...
>
> Best Regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100-3329
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of steve weir
> Sent: Tuesday, September 02, 2014 7:04 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: options for reducing EMI
>
> This is another infamous:  "It depends".
>
> First:  Will any combination of anticipated measures yield a solution that
> meets both your SI and EMC requirements?
> Second: Do you prioritize margin to SI or EMC, or split them?
>
> It sounds like you have a design that has failed EMC.  Before twiddling
> anything that you can look at where you are failing and how badly.
>
> TX swing can only reduce noise in the best case dB for dB.  So, if you
> just need a couple of dB to squeak by and have the link budget, it is an
> option.
> SSC can buy up to 10dB on the clock and harmonics.
> Edge rate could help if you have resonance issues.  Otherwise, it is
> similar to fiddling with the Tx swing.
>
> Steve
> On 9/1/2014 1:43 PM, Chen, Sherman wrote:
> > Hi SI Gurus,
> > We are considering the following options in order to reduce the EMI of
> one of our boards, which is mainly caused by the PCIe Gen3 link:
> >
> > 1.       Reducing TX swing.
> >
> > 2.       Turn on SSC.
> >
> > 3.       Slowing down edge rate.
> > While we are running test to verify which option will bring us the best
> result & least impact, any comments or suggestions from those who had
> experiences on this matter?
> >
> > Best Regards,
> >
> > Sherman Chen
> > Signal Integrity
> > EMC Global Hardware Engineering
> > Tel: +86 21 60951100-3329
> >
> >
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> --
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