[SI-LIST] Re: options for reducing EMI

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: "Chen, Sherman" <sherman.chen@xxxxxxx>, jackle zheng <zheng.jackle@xxxxxxxxx>
  • Date: Sat, 06 Sep 2014 04:17:30 -0700

LFSRs are a throwback to SONET voice coding with a short 7 bit LFSR.  
Malicious payloads established the need to do something better.  The 
preamble and big coupling capacitor style of 64/66, 128/130, and 128/132 
is a solution that has lower channel overhead than 8b/10b, but seems 
very brute force to me.  It carries nasty side effects in the channel 
when one tries to go really fast.   In a world where 8Gbps are 
pedestrian, imposing low frequency problems is a crime against 
engineering sanity.
Steve
On 9/5/2014 9:44 PM, Chen, Sherman wrote:
>
> That’s correct, Jackle. In PCIe the scrambling is on in default so it 
> should not be the contributor to the issue.
>
> However this  remind me of another long time standing question – How 
> the 128/130b coding achieve DC balance?
>
> In PCIe Gen2 on the transmitter end the data is first scrambled then 
> 8b/10b encoded. In my understanding the main purpose of scrambling are
>
> 1.Randomizing the data pattern hence disperse the spectrum.
>
> 2.Eliminate long runs of 1s or 0s so as to maintain the transition ratio.
>
> And the usefulness of 8b/10 are
>
> 1.Achieving DC balance & 50% transition ratio within 10bit span.
>
> 2.Other features such as control symbols, error detection, etc.
>
> When it came to Gen3 the 8b/10b was replaced by 128b/130b with the 
> stages of scrambler LFSR raised from 16 to 23. Since the 128b/130b 
> encoding literally does nothing in minimizing running disparity, I 
> guess the 23-stage LFSR achieves an nearly equivalent effect in terms 
> of as the 16-stage LFSR +  8b/10b encoding? Also there is another 
> changes such as increasing the coupling cap from 75-200nF to 
> 176nF-265nF which looks to me this change is to accommodate the 
> increased running disparity…
>
> Are above conjectures true?
>
> Best Regards,
>
> *//*
>
> */Sherman Chen/***
>
> Signal Integrity
>
> EMC Global Hardware Engineering
>
> Tel: +86 21 60951100-3329
>
> *From:*jackle zheng [mailto:zheng.jackle@xxxxxxxxx]
> *Sent:* Thursday, September 04, 2014 5:09 PM
> *To:* Chen, Sherman
> *Cc:* Scott McMorrow; weirsi@xxxxxxxxxx <mailto:weirsi@xxxxxxxxxx>; 
> si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
> *Subject:* Re: [SI-LIST] Re: options for reducing EMI
>
> scramble also can decrease EMI. i was testing the HDMI 2.0 UD60 
> signals. Before sending, the data was scrambled for decreasing EMI
>
> 2014-09-04 5:27 GMT+08:00 Chen, Sherman <sherman.chen@xxxxxxx 
> <mailto:sherman.chen@xxxxxxx>>:
>
> Understood. That's why we've been keeping SSC off. Thanks.
>
> Best Regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100-3329
>
> From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx 
> <mailto:scott@xxxxxxxxxxxxx>]
> Sent: Wednesday, September 03, 2014 9:31 PM
> To: Chen, Sherman
> Cc: weirsi@xxxxxxxxxx <mailto:weirsi@xxxxxxxxxx>; 
> si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
> Subject: Re: [SI-LIST] Re: options for reducing EMI
>
>
> Chen
>
> You can certainly do that, but it's a band aid for whatever the actual 
> problem is.  You should just not be radiating at 8 GHz.
>
> Regards,
>
> Scott
>
>
> Scott McMorrow
>
> Teraspeed(r) Consulting - A Division of Samtec
>
> 16 Stormy Brook Rd
> Falmouth, ME 04105
> (401) 284-1827 <tel:%28401%29%20284-1827> Business
> http://www.teraspeed.com
>
> On Wed, Sep 3, 2014 at 9:20 AM, Chen, Sherman <sherman.chen@xxxxxxx 
> <mailto:sherman.chen@xxxxxxx><mailto:sherman.chen@xxxxxxx 
> <mailto:sherman.chen@xxxxxxx>>> wrote:
> Thanks, Steve.
> The freq. exceeding the EMI margin is 8GHz. Enabling SSC should help 
> on that I think.
> Any impact & precaution for turning SSC on? Looks there would be no 
> big issue since all our chip vendors claims their products work fairly 
> well with SSC on...
>
> Best Regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100-3329
>
>
> -----Original Message-----
>
> From: si-list-bounce@xxxxxxxxxxxxx 
> <mailto:si-list-bounce@xxxxxxxxxxxxx><mailto:si-list-bounce@xxxxxxxxxxxxx 
> <mailto:si-list-bounce@xxxxxxxxxxxxx>> 
> [mailto:si-list-bounce@xxxxxxxxxxxxx 
> <mailto:si-list-bounce@xxxxxxxxxxxxx><mailto:si-list-bounce@xxxxxxxxxxxxx 
> <mailto:si-list-bounce@xxxxxxxxxxxxx>>] On Behalf Of steve weir
> Sent: Tuesday, September 02, 2014 7:04 AM
>
> To: si-list@xxxxxxxxxxxxx 
> <mailto:si-list@xxxxxxxxxxxxx><mailto:si-list@xxxxxxxxxxxxx 
> <mailto:si-list@xxxxxxxxxxxxx>>
> Subject: [SI-LIST] Re: options for reducing EMI
>
> This is another infamous:  "It depends".
>
> First:  Will any combination of anticipated measures yield a solution 
> that meets both your SI and EMC requirements?
> Second: Do you prioritize margin to SI or EMC, or split them?
>
> It sounds like you have a design that has failed EMC. Before twiddling 
> anything that you can look at where you are failing and how badly.
>
> TX swing can only reduce noise in the best case dB for dB.  So, if you 
> just need a couple of dB to squeak by and have the link budget, it is 
> an option.
> SSC can buy up to 10dB on the clock and harmonics.
> Edge rate could help if you have resonance issues. Otherwise, it is 
> similar to fiddling with the Tx swing.
>
> Steve
> On 9/1/2014 1:43 PM, Chen, Sherman wrote:
> > Hi SI Gurus,
> > We are considering the following options in order to reduce the EMI 
> of one of our boards, which is mainly caused by the PCIe Gen3 link:
> >
> > 1.       Reducing TX swing.
> >
> > 2.       Turn on SSC.
> >
> > 3.       Slowing down edge rate.
> > While we are running test to verify which option will bring us the 
> best result & least impact, any comments or suggestions from those who 
> had experiences on this matter?
> >
> > Best Regards,
> >
> > Sherman Chen
> > Signal Integrity
> > EMC Global Hardware Engineering
> > Tel: +86 21 60951100-3329
> >
> >
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> --
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