[SI-LIST] Re: optimize Equalization and De-emphasis settings
- From: "Stephen Zinck" <szinck1@xxxxxxxxxxxx>
- To: "'Dmitriev-Zdorov, Vladimir'" <vladimir_dmitriev-zdorov@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 24 Nov 2010 10:44:56 -0500
Hi Vladimir,
I agree with what you stated below.
I mentioned my s-parameter concatenation flow, just for informational
purposes, as it is an extension of the setting optimization that is provided
by the tools from Altera and Broadcom, in that these tools require a single
S-parameter file.
As far as Gert's specific case, I think he, unfortunately, needs to handle
each silicon-PCB-silicon case individually. And yes, some behavior will not
be passed on to the next stage. The tools are not there for this behavior.
But as long as all requirements are met at each receiver, given worst case
patterns, PVT corners, TX and RX settings, etc., the overall design will be
robust, even though it is analyzed in stages...
Best regards,
Steve
Stephen P. Zinck
High-Speed Signal Integrity Consulting
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Dmitriev-Zdorov, Vladimir
Sent: Tuesday, November 23, 2010 05:46 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: optimize Equalization and De-emphasis settings
Hi Steve,
As was stated in the original question: "I'm looking for some technique or
algorithm to determine the desired amount of equalization just by examining
each silicon's input signal". Therefore I think that the purpose was to find
equalization in every analog portion separately. Digital processing in the
silicon itself is not involved.
We cannot generate the combined 4-port model that includes switches and
channels, or equally we shouldn't produce combined model for the channels
separated by switches. Switch is not something that can contribute to the
transfer function or S-parameters, because it is a heavily non-linear
transformation - similar to A/D converter.
Logically, it also does not make sense to combine links because if the first
switch fails (produces incorrect bit) all others should fail too, and no
equalization in the subsequent links will help. Therefore equalization
should be constructed separately for each analog link.
In Hyperlynx FastEye, there is a possibility to find optimal set of FFE and
DFE taps, given the channel schematic, S-parameters or its equivalent step
or pulse response.
Vladimir
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Stephen Zinck
Sent: Tuesday, November 23, 2010 6:28 AM
To: 'Havermann, Gert'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: optimize Equalization and De-emphasis settings
Hi Gert,
If you are using Altera or Broadcom, they have applications that automate
this process (other vendors may also have this capability). All you do is
provide a 4-port S-parameter model of your system and the tool will tell you
the required settings for the most open eye. Pretty cool.
I use SIWave from Ansoft to extract all the features for a particular link
(BGA pads, traces, accurate via models, passive pads, etc.). The output of
this tool is 4-port S-parameters. If multiple system S-parameter files are
required for each element (switch-backplane-switch), these models are then
concatenated in Ansoft's Designer SI. This tool can accurately concatenate
S-parameter files into a single file for the entire system.
Best regards,
Steve
Stephen P. Zinck
High-Speed Signal Integrity Consulting
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Havermann, Gert
Sent: Tuesday, November 23, 2010 07:05 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] optimize Equalization and De-emphasis settings
Dear Experts,
is there any way to determin the optimum settings for Equalization and
De-emphasis in a channel simulation?
Situation: I'm running simulations of cascaded channels
(driver-PCB-switch-PCB-switch-PCB-reclocker-PCB-Receiver). Each silicon
has analog equalization and de-emphasis, only some have ECR, thus i
can't just simulate section by section.
Simulation takes very long, thus I would like to start with optimum
settings. I'm looking for some technique or algorithm to determin the
desired amount of equalization just by examining each silicon's input
signal (Eye, spectrum, timing...).
Any thoughts or paper reference is appreciated.
BR
Gert
http://www.mesago.de/de/SPS/home.htm
Besuchen sie uns auf der SPS/IPC/Drives in Nürnberg, vom 23. - 25. November
2010, in Halle 10, Stand 130.
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