[SI-LIST] Re: op-amp compensation capacitor in digital cmos process
- From: Bi Han <mike_bihan@xxxxxxxxxxxx>
- To: Bill.Cohen@xxxxxxxxxxxxxxxx, List` Si <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Jul 2003 09:23:11 +0800 (CST)
Bill:
Thanks for your information!
I agree that MOS gate cap is a good idea.
But I may not be able to guarantee the working range of MOS cap in strong
inversion mode because the gain of the op-amp will be very high.
Meanwhile, there is no triple well process, so all nmos's well is connected to
substrate, pmos to VCC.
What should I do?
Bill.Cohen@xxxxxxxxxxxxxxxx wrote:
Han,
It may not be a great idea but I compensate all my opamps with MOS gate
capacitors. Just make sure the device is in saturation otherwise you will
get too much series resistance to the thin oxide device. If it is a rail to
rail opamp you may need to used Both NMOS and PMOS devices to keep at least
one device active depending on the common mode. Also, you will only be able
to use the device in the well if you need a compensating device with one
end not tied to the power supply.
Bill Cohen
Toshiba America
Bi Han
com.cn> cc:
Sent by: Subject: [SI-LIST] op-amp compensation capacitor in digital cmos
si-list-bounce@fre process
elists.org
07/15/2003 07:34
AM
Please respond to
mike_bihan
hi, experts:
I am on a project designing high speed limiter in digital cmos process. I
need to design some op-amp as controlling circuits.
So, I need capacitor to compensate them to stable. But, in my digital cmos
process(1p6m), there will be no MIM/PIP capacitor, so I can not compensate
the op-amp!!
Any people have good idea?
Thanks, Han
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