[SI-LIST] Re: (no subject)
- From: scott <scott@xxxxxxxxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx
- Date: Mon, 11 Mar 2002 23:41:29 -0800
Chris and I are in agreement here. EM fields are lazy. They always take
the path
of lowest energy, which is also the path of lowest impedance. If a
capacitive path
is lower impedance than an inductive path, image currents will prefer
the capacitive
path. The interplane capacitance often takes the majority of image
current mismatches.
The trade-off is that the additional interplane current also causes
increased noise.
These issues occur at the boundary where the signal transitions from one
reference to
another. Power will be injected into the interplane capacitance and
some impedance
mismatch will be seen at the boundary. At sufficiently high enough
frequencies, planar
resonances can be excited. But for DDR operating frequencies, this is
not a major issue.
There will be some edge rate degradation as the signal crosses the
transition boundary.
regards,
scott
--
Scott McMorrow
Principal Engineer
SiQual Interconnect Engineering
18735 SW Boones Ferry Road
Tualatin, OR 97062-3090
(503) 885-1231
http://www.siqual.com
Chris Cheng wrote:
>Here we go again. Unless you are dealing with 100ps edges (unlikely if you
>have 2.5V signals), the image current on the 5V plane will return through
>the plane capacitance between the 5V and gnd pair that sandwich the
>stripline. Discrete decoupling caps or even planes on the other side of the
>5V plane will not have low enough impedance to make a difference. For normal
>SSTL DDR buses, the plane capacitance should have low enough impedance for
>the image current from the 5V plane to return through the gnd plane. No big
>issue.
>
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