[SI-LIST] measuring voltage stress on a component on a PCB during ESD and design rule violation in many new designs
- From: Doug Smith <doug@xxxxxxxxxx>
- To: Si-List <si-list@xxxxxxxxxxxxx>, emc-pstc <emc-pstc@xxxxxxxx>
- Date: Mon, 11 Jul 2011 09:26:08 -0700
Hi Everyone,
Just posted my latest Technical Tidbit:
Technical Tidbit - July 2011
Measuring ESD Stress on a PCB
(When Conventional Measurements Don't Work)
This month's Technical Tidbit describes a useful method of measuring stress
voltages on a PCB under ESD conditions.
Abstract: Measuring voltage stress on components on a PCB under ESD
conditions can be difficult as the ESD noise can inject error in the
measurement. Often this error is larger than the voltage of the stress to be
measured. A method of measuring voltage stress is discussed that has very
high common mode rejection and low ESD induced error.
The link is: http://emcesd.com/tt2011/tt070811.htm[1]
Also my latest Blog on a common design rule violation and its effects is at
http://circuitadvisor.com[2] .
Doug
-- ------------------------------------------------------- ___ _ Doug Smith
\/ ) P.O. Box 1457 ========= Los Gatos, CA 95031-1457 _ / \ / \ _ TEL/FAX:
408-356-4186/358-3799 / /\ \ ] / /\ \ Mobile: 408-858-4528 | q-----( ) | o |
Email: doug@xxxxxxxxxx[3] \ _ / ] \ _ / Website: http://www.dsmith.org[4]
-------------------------------------------------------
--- Links ---
1 http://emcesd.com/tt2011/tt070811.htm
2 http://circuitadvisor.com
3 mailto:doug@xxxxxxxxxx
4 http://www.dsmith.org
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