[SI-LIST] Re: measuring switching thersholds

  • From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 18 Aug 2006 00:03:19 -0400

There is no guarantee that any two inputs on any device have the same
switching threshold.

In CMOS with single-ended inputs, it depends on the relative sizes of the P
and N channel input FETs, which could be sized differently for CLK inputs
and NAND inputs ... though chances are the designers tried to use the same
ratios to get similar input switching levels.


----- Original Message ----- 
From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, August 17, 2006 08:23 AM
Subject: [SI-LIST] measuring switching thersholds

> =20
> I need to establish the voltage point where a flop's clock input allows
> the read of its D input.=20
> There is some combinatorial logic in the same device. I was thinking
> that it would be easier to measure the switching threshold on an "and"
> gate.=20
> The question is, if I measure the switching threshold on an "and" gate
> will it be the same as the switching threshold on a flop's clk input?
> both are in the same device and have the same technology.=20
> (visualizing a flop as a circuit containing a bunch of nand gates, I'm
> guessing it is the same, but I'm not sure.)
> thanks.
> Jim Peterson
> Honeywell

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