[SI-LIST] measure the S parameters between the embedded layer

  • From: Istvan Novak <istvan.novak@xxxxxxx>
  • To: bearsky_2008@xxxxxxx
  • Date: Thu, 23 Jun 2011 21:41:47 -0400

Hi Vincent,

Embedded thin laminates can be measured from the surface easily with
the two-port shunt-through connection.  You connect one port to the top,
another port to the bottom side of the same through holes and measure
S21 with the VNA.  If you prefer using SMA connectors, you have to
attach them to the board at the same location, one on the top side and
one on the bottom side.  This way you will measure the self impedance
at the location of the connectors.  You could also measure with probes
or SMA connectors both attached to the same side at different locations,
but this way you will measure transfer impedance.

You can read more about the setup, connection, instrumentation and measured
results in some of the papers posted at www.electrical-integrity.com.
You can start with the paper from DesignCon99, High-Performance Systems
Design Conference, Santa Clara, CA, Feb 1-4, 1999
"Probes and Setup for Measuring Power-Plane Impedances with Vector-Network
Analyzer"

Regards,

Istvan Novak
Oracle



********************************************************************************************
Subject: [SI-LIST] measure the S parameters between the embedded layer
From: "hrzhu" <bearsky_2008@xxxxxxx>
Date: Fri, 24 Jun 2011 08:27:48 +0800
To: "si-list all" <si-list@xxxxxxxxxxxxx>

Hi experts,

I'm desing a test board by using emdedded capacitor which the thickness 
is only 14um , the whole board is four layer, while the emdedded 
capacitor layer in the center and two 0.8mm FR4 layer loate top and 
bottom repectively.

The question is I want to measure the S parameters of the embedded 
capacitor, that is , the test ports locate in between the second and 
third metal latey. However, the actual test ports of SMA locate in the 
top metat layer.

So,I need to introduce the signal from second layer to top layer. I have 
tried to use 4 via around test port, however maybe the embedded capcitor 
is very thin and the top FR4 layer is thicker relatively, the simulated 
result is poor.

I wonder any experts could give some advice? Thanks a lot!

Vicent


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