[SI-LIST] measure the S parameters between the embedded layer
- From: "hrzhu" <bearsky_2008@xxxxxxx>
- To: "si-list all" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 24 Jun 2011 08:27:48 +0800
Hi experts,
I'm desing a test board by using emdedded capacitor which the thickness is only
14um , the whole board is four layer, while the emdedded capacitor layer in the
center and two 0.8mm FR4 layer loate top and bottom repectively.
The question is I want to measure the S parameters of the embedded capacitor,
that is , the test ports locate in between the second and third metal latey.
However, the actual test ports of SMA locate in the top metat layer.
So,I need to introduce the signal from second layer to top layer. I have tried
to use 4 via around test port, however maybe the embedded capcitor is very thin
and the top FR4 layer is thicker relatively, the simulated result is poor.
I wonder any experts could give some advice? Thanks a lot!
Vicent
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
