[SI-LIST] Re: matching within 1 mil

  • From: "Stephen Zinck" <signalintegrity@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 1 Jun 2007 14:09:14 -0400

I echo this...

To my way of thinking, the first step should be understanding the interface 
from a margin perspective. Length matching, trace spacing, stackup design, 
layer usage (and the plethora of other tools we use - termination 
methodology, topology, etc.) should be just that... tools a designer can 
utilize to squeak ps of margin out of design, especially with high-speed 
memory interface margins today being under 100ps. But if plenty of margin 
exists, the length matching rules, etc. should be moderated to ease the 
layout design, saving time and money. Science should have an important role 
in the decision making process...

Steve

Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com


----- Original Message ----- 
From: "Kihong Kim" <joshuakh@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, June 01, 2007 11:43 AM
Subject: [SI-LIST] Re: matching within 1 mil


>I agree on Jeff's view quite happily.
> This is about the optimization among physical constraints including cost.
>
> Signal integrity is not pursuing THE best signal quality.
>
> I think it should pursue most optimal signal quality under the imposed
> constraints.
>
>
> Kihong Joshua Kim
>
> SI in Photonics and Electronics
>
>
>
>>
>>
>> On 6/1/07, Loyer, Jeff <jeff.loyer@xxxxxxxxx > wrote:
>> >
>> > I think folks are missing Bill's point.  I don't think he's saying that
>> > the design is going to break at 2 mils routing difference, only that he
>> > can easily attain a maximum 1 mil delta, so he uses that as his
>> > constraint.  If his CAD folks balked at that number, he'd probably
>> > adjust accordingly and, if it got close to having significant impact,
>> > would do a more detailed analysis.
>> >
>> > This is very similar to what we've done for common-clock FSB signals:
>> > tell our CAD folks to match them within 10 mils (or some number), even
>> > though we know we can absorb more.  But, 10 mils is easily attainable,
>> > and guarantees essentially no skew due to length differences.  Granted,
>> > it's a little more work on CAD's part, but the tradeoff is I don't have
>> > to do a grand analysis to figure out exactly how close they HAVE to be
>> > matched, and then worry about whether my analysis was correct (and
>> > require subsequent validation in the lab, etc.).=20
>> >
>> > This is about compromises, and where you put your energy into in-depth
>> > analysis.  If you can easily do 1 mil spacing, no problem.  It's a
>> > little tighter than I'd generally specify, but it's not absurd, either.
>> > If you're using an auto-router (that's surprising to me, I didn't think
>> > leading-edge designs could use them), you probably have different
>> > constraints.
>> >
>> > Jeff Loyer
>> > ------------------------------------------------------------------
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>>
>
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