[SI-LIST] Re: mDDR (200MHz) without Series Termination

  • From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx, "hw_si@xxxxxxxxxxxxxx >> ranjith" <hw_si@xxxxxxxxxxxxxx>
  • Date: Wed, 10 Nov 2010 22:02:08 +0100

Hello,
as Cathereine already mentioned:
There is a very high possiblitly that you will get problems with
overshoots when working without serial termination.
For DQ signals (writes) and CA signals you need to take a close look on
the available drivestrength settings on the TI controller, and even not
checking the datasheet I would guess you have a problem in violating the
JEDEC overshoot spec without a serial termination!
For the Reads you also need to check the Controller overshoot specs, but
I guess you are in a similar situation there.


A simulation of this setup to get a fast indication is done quite fast
and should not really require a lot of effort. As X-talk can be really
high on such an unterminated bus I would do at least a 5 coupled line
simulation (3 coupled lines only if you have quite large spacing between
the lines).

Best Regards

Hermann





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Hermann Ruckerbauer
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schrieb Xu, Catherine (ICS):
> Hi, Ranjith,
>
> mDDR DRAM parts with 200 MHz clock can have rise time as fast as ~200ps, so 
> 2-inch trace will exhibit Txline effect. In addition, please consider mDDR 
> does not have ODT and rely on Txline Z0 matching driver's source impedance. 
> So you'd expect close to full reflection at the receiver side. This present 
> overshoot and increases xtalk. You want to check through simulation or 
> measurement that the waveshape at receiver side still meet JDEC spec for 
> timing as well as voltage spec with sufficient margin( especially overshoot 
> spec). On EMC side, this noise consists of harmonics of 200 MHz will need to 
> find a sizable antenna to cause RE failure. It is relatively easy to mitigate 
> by either avoid the noise coupling to an antenna structure ( cable/metal 
> plate, etc), or filter cables whose signal might pick up noise from mDDR 
> block.
>
> Hope it helps!
>
> Catherine Xu
> __________________________________
> Lead HW Design Engineer, Ph.D
> HP ICS  CHIL - San Diego
> __________________________________ 
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of steve weir
> Sent: Wednesday, November 10, 2010 7:00 AM
> To: Embedded
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: mDDR (200MHz) without Series Termination
>
> The best thing to do is run a simulation that includes models for the 
> parts that you are using.  If you do not have simulation capability, 
> then at least look at the rise and fall times in the models to estimate 
> your situation.
>
> Steve.
>
> Embedded wrote:
>> Dear Experts,
>> We are using TI AM37x processor with mDDR interface in our design.
>>
>> The mDDR maximum clock frequency is 200MHz.
>>
>> In our PCB Layout, we are placing mDDR chip close to AM37x CPU 
>> and the maximum trace lenghth between mDDR and CPU is less than 2 inch 
>> (Approximately 1.8 inch) only.
>>
>> In this case, do we need provide series termination (trace length less than 
>> 2 inch only)?
>>
>> Will there be any EMI issues if we are not using series termination?
>>
>> Looking forward your response. Thanks in Adavnce.
>>
>> Thanks and Regards
>> Ranjith
>>
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