[SI-LIST] Re: logic analyzer probes on LVDS
- From: "Robert Sefton" <rsefton@xxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 26 Mar 2002 10:28:05 -0800
Ellis -
This is very doable if you choose the right connectors and logic analyzer
probes, and route the signals correctly. There are differential connector +
probe solutions out there with < 2-3pF of total load. Check with HP and
Tektronix.
rjs
----- Original Message -----
From: <evillaf@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, March 26, 2002 9:13 AM
Subject: [SI-LIST] logic analyzer probes on LVDS
> Gentlemen,
>
> I have a SPI4 bus running at 155 MHz DDR (LVDS) between
> two Xilinx FPGAs that are placed right next to each
> other. My boss wants to put LA headers on this bus
> (positive signals only). Any comments?
>
> Thanks in advance.
> Ellis
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