[SI-LIST] Re: load of a High-impedant I/O on a bus
- From: James_R_Jones@xxxxxxxx
- To: nico.fleurinck@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 3 Feb 2003 08:04:37 -0600
The answer to that question, as I understand it, is yes. Tristating a
buffer can change the capacitance looking into the pin. And clearly, it
changes the impedance looking into the pin. If you really want to know how
much the impedance changes, and at what frequency, then I would recommend
talking to the manufacturer of the component. Also, you could get the
IBIS/Spice model and study it in simulation.
James R. Jones
Dell
-----Original Message-----
From: Nico Fleurinck [mailto:nico.fleurinck@xxxxxxxxxxxx]
Sent: Monday, February 03, 2003 2:30 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] load of a High-impedant I/O on a bus
Importance: High
Dear experts,
For my design i need to trade-off the use of a data-bus buffer.
I know that the data bus of the memory chips are three-state I/O's.
But my question is, what is the load of an I/O pin on a bus when the device
is in a high-impedant state?
Does the high impedant state of an I/O pin effects his Cin??
I need to know this because i need to calculate the total amount of
capacitive load on the data bus.
If you know an answer, please let me know.
Best Regards,
Nico
Nico Fleurinck
Junior Design Engineer
VERHAERT Satellites & Platforms
Hogenakkerhoekstraat 21
B-9150 Kruibeke
Tel : +32 3 250.1984
Fax : +32 3 254.1008
e-mail : nico.fleurinck@xxxxxxxxxxxx
Visit us : www.verhaert.com
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