[SI-LIST] Re: jitter measurements on clock
- From: "Al Neves" <al@xxxxxxxxxxxxxxxxx>
- To: "'prasad'" <hariprasad.palli@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Aug 2010 11:16:41 -0700
A TIE has the ability to directly make period measurements (you can extract
period jitter such as Variance from this data) and accumulated, phase
jitter, or absolute jitter which is multiple numbers of periods of jitter.
The PCI Express Gen II document discusses 3 common jitter catagories:
period jitter, phase jitter, and cycle-cycle.
If you make a PLL jitter measurement on N-periods,
P(n)=s(n)-x(n-N), take the Fourier transform, the Power spectrum is
proportional to phase noise^2*sin^2(N/2)
This is the naturally occurring filter with an accumulated jitter
measurement that shapes the jitter power spectrum. The filter or
mathematical relationship is relevant when relating period to phase jitter.
Two good refs: "Spectral Analysis of Time Domain Phase Jitter
Measurements", Moon
And, "Jitter in Ring Oscillators" by John McNeill
Going back to Steve's comment, what are you trying to do, what market are
you addressing, and what compliance spec is relevant to you for your clock
characterization? Unfortunately it isn't as ez as hitting "magic button" on
your EzJitt software.
Period measurements of jitter are more applicable for digital circuits that
must maintain a set up time, or some ciritical timing for data latching from
one clock edge to the next. Accumulated or Phase jitter is applicable for
A/D converter clock Effective Number of Bits (ENOB) and telecom/datacom
where the clock drives either TX, RX or both and you want a min BER.
Accumulated or Phase jitter is also useful for PLL jitter transfer analysis,
VCO and PLL design, setting filter constants etc., As I stated in an
earlier mail, Accumulated Jitter analysis can compliment direct Phase Noise
Analysis of PLL clocks.
Products for the Signal Integrity Practitioner
Alfred P. Neves
Founder - Engineer - Business Development
(503) 718 7172 Office
(503) 679 2429 Mobile
735 South East 16th Ave.
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of prasad
Sent: Monday, August 16, 2010 5:36 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: jitter measurements on clock
hi All,
what is a "TIE filter" in the jitter measurement application? and how does
it affect measurements?
thanks,
hari prasad
On 14 August 2010 06:15, Chris Cheng <Chris.Cheng@xxxxxxxx> wrote:
> I agree we need to be careful about interpreting Rj data from scope
> software such as EzJIT.
> Chances are your clock source is generated from a PLL and your receiving
> chip is also a PLL.
> You need to at least input your receiving PLL loop bandwidth to EzJIT type
> of software.
> Jitter transfer is a function of your PLL loop bandwidth and the effective
> Rj after passing the ideal PLL is also dependent on the loop bandwidth.
> And if your receiver PLL bandwidth dropped below the reference clock PLL
> loop bandwidth, the Tj together with your Pj will grow.
> Chris
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of steve weir
> Sent: Thursday, August 12, 2010 1:40 PM
> To: prasad
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: jitter measurements on clock
>
> Prasad, what you do depends on what you want to know. Before worrying
> so much about which buttons to push in the software, I think you need to
> clearly establish your goals.
>
> Do you want to know if the clock really meets its specification? Then
> you need to reproduce equivalent test conditions and measurement
> extraction as used by the clock manufacturer.
>
> Do you want to inspect incoming parts? Then you can less rigorous
> testing and extraction.
>
> Do you want to compare clocks from different manufacturers to make
> product selection? Then you need to not only test to the vendor spec,
> but qualify the clock under the conditions you wish to apply it.
>
>
> Steve.
> prasad wrote:
> > hi all,
> > thank you very much for your suggestions.
> >
> > from all the discussions , what i understand is ,
> >
> > 1.clock signal is assumed to have very negligible determinsitc jitter
> > 2. Manufacturers always specify the RJ of the same
> >
> >
> > if i need to verify this spec , i need to measure the TIE RMS (AC) or
> use
> > the RJ and DJ separation wizard to extract the RJ value verify.
> >
> >
> > please comment.
> >
> >
> > once again thank you very much for all your inputs.
> >
> >
> > Best Regards,
> > hari.
> >
> > On 13 August 2010 00:02, T.K. Jeon <tkjeon@xxxxxxxxxxx> wrote:
> >
> >
> >> Hi Hari,
> >>
> >> Simply taking the rms value of TIE won't give you random jitter. For
> better
> >> measurement, you should subtract the average TIE from your real time
> TIE,
> >> and take AC rms value of the resulted value. This would give you more
> >> accurate value than the rms of the real time TIE. However, the final
> value
> >> by using this way is not pure random jitter, i.e. it includes RJ plus
> >> uncorrelated PJ. Therefore, you should use other technique to separate
> the
> >> PJ component from your TIE measurement.
> >>
> >> Regards,
> >> TK
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
> ]
> >> On Behalf Of prasad
> >> Sent: Wednesday, August 11, 2010 10:34 AM
> >> To: si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] jitter measurements on clock
> >>
> >> hi All,
> >> normally when we look at the data sheets of a clock signal for the
> jitter
> >> number, they usually specify it a RMS jitter.
> >>
> >> i understand from the basics that , only random jitter is quantified as
> >> RMS.
> >> i am not sure why there is only random jitter in the clock. is the
> >> Deterministic component is negligible?
> >>
> >> in that case, using our EzJIT plus software, if i want to measure this
> spec
> >> of a the clock, what would be my measurement?
> >>
> >> is it ok, if i measure the TIE of the clock and take the RMS of the TIE
> >> trend?
> >>
> >>
> >> thanks,
> >> hari
> >>
> >>
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> --
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