Vijay, Not sure I am correctly visualizing your architecture, but I assume you mean you have 5 DDR SDRAMs on a board, making up a single rank data bus, each with its own clock.=20 The clocks do need to be matched for several reasons. One is that there is generally a common set of CTRL and ADR/CMD signals bussed across all the SDRAMs in a rank. So you need a common CLK reference to do setup and hold timing against. Same is true for ADR/CMD, but this path is sometimes less critical depending on whether you are running 1N or 2N timing on ADR/CMD bus. Any CLK skew between devices will result in loss of overall timing margin. Since CTRL to CLK margin is usually one=20 of the critical timing paths, aanything you can do to limit clock skew is worth doing. The other possible issue, and I don't know enough about the controller you are using, or the overall clocking architecture to say with certainty, but there is usually an outer loop timing path on reads which requires a known relationship between the master controller clock reference and the strobe timing for all byte lanes. If your byte lanes are skewed due to varying clock lengths to the SDRAMS, then the=20 byte lanes come back out of phase and this outer loop timing path is harder to optimize. I'm guessing this is one reason the app note is telling you to match all cloock lengths. Our controller guidleines also require this.=20 As a general rule it is always preferred to keep all clocks length matched. The spec you quoted of 20 mils is a good target. =20 Brian P. Moran Intel Corporation=20 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Vijay Sivasubramanian Sent: Tuesday, May 23, 2006 4:37 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] is clock pair-to-clock pair matching required in DDR? Guys -- =20 We have designed a board with a Freescale powerQUICC processor. It has 6 separate DDR clock outputs. We have 5 DDR on-board chips. My question is - do we have to match the length of each of the 5 clock-pairs? I don't quite understand the need for matching the individual clocks, but this was given in one of the Freescale app notes. The app note recommends 20mils matching within each of the clock pairs. We have matched the individual clock pair w.r.t the corresponding DQS within 20mils and DQS to corresponding clock within 250mils. I feel as long as the Clock-DQS-Data relationship is maintained, the clock pair-to-pair matching might not be required. Would greatly appreciate your help on this. =20 Thanks Vijay GDA Technologies Ltd., India www.gdatech.com =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu