[SI-LIST] Re: is 8b/10b too much or too little?
- From: "Zabinski, Patrick J." <zabinski.patrick@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 11 Sep 2001 13:28:28 -0500
Tim,
Thanks; this *is* what I'm after. I'll see if I can
find a copy of the reference to learn more about the underlying
analysis, but this will help me engineer an application-specific
solution rather than just picking one and assuming it works.
Thanks,
Pat
>
> Pat,
>
> This is from Dally and Poulton Digital Systems Engineering
>
>
> Max number of bit cells between transitions is given by
>
> N = tpd
> ___
>
> dF * tc^2
>
>
> tpd = timing margin budgeted to drift
> dF = maximum frequency difference (Function of PLL)
> tc = bit cell time
>
>
> The maximum frequency difference is a function of PLL
> bandwidth. A wider
> bandwidth allows more drift
> between pump cycles, but allow the pll to lock into frequency changes
> faster. So, your question has to be taken
> in the context of the pll filters. If you want to be able to
> track faster
> changes (i.e. more jitter tolerance)
> you need more edges. If you are certain your system doesn't
> jitter too
> much, then you can get away with
> lower edge rates.
>
> Is this the kind of stuff you are looking for? Let me know
> and I will dig
> up what I can.
>
>
> Tim
>
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