Hi all Had someone done the simulation the signal integrity of the vertex II of xilinx fpga with Hspice, I have downloaded the Hspice model of the vertex II, but the model puzzle me. I do not know how to design the netlist of Hspice with the the model, I just want to use the vertex II model downloaded and rlgc circuit from my PCB for SI simulation, could someone give me some guid,thanks all ! ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu