[SI-LIST] high speed digital design decoupling question
- From: "Nico Fleurinck" <nico.fleurinck@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Apr 2003 08:29:45 +0200
Dear all,
Is there a potential problem possible when you have a lot of high speed
digital IC's in parallel on the same voltage supply track and you use low
ESR decoupling caps? What can happen when you do that?
Does any one has some reference documentation about decoupling of high speed
IC's?
Are there rules of thumb to follow for decoupling?
Any information is more then welcom!
Many thanks in advanced.
Best regards,
Nico
Nico Fleurinck
Junior Design Engineer
VERHAERT Satellites & Platforms
Hogenakkerhoekstraat 21
B-9150 Kruibeke
Tel : +32 3 250.1984
Fax : +32 3 254.1008
e-mail : nico.fleurinck@xxxxxxxxxxxx
Visit us : www.verhaert.com
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