[SI-LIST] Re: ground planes at top / bottom layer

  • From: olaney@xxxxxxxx
  • To: bernd.schuster12@xxxxxxxxxxxxxx
  • Date: Tue, 30 Dec 2008 14:55:19 -0800

Outside ground planes are a classic means of controlling EMI from the
board proper, among other benefits.  However they are certainly in the
way if you are probing traces for debug.  The Atmel evaluation boards are
designed for probing and to keep cost low, so are no guide to what should
be done for your project.  Of course, adding outside planes changes the
impedance calculations for traces underneath.  Also, I would never use an
outer plane for VCC or anything other than ground.  To do so begs for
disaster.

Regards,

Orin Laney

On Tue, 30 Dec 2008 21:24:26 +0100 "bernd schuster"
<bernd.schuster12@xxxxxxxxxxxxxx> writes:
> Hi,
> I`ve one small question about the usage of ground planes at the top 
> and
> bottom layer. I thought it would be great to use them, but the atmel
> evaluation boards (for example) do not use an ground plane on the 
> top layer
> or bottom layer. They use for example an 8 layer stack design (where 
> layer 5
> is a vcc plane and layer 2 is a ground plane).
> 
> Are there any disadvantages of using ground planes at the top / 
> bottom
> layer? In my first 4-layer board I use ground planes at the top, 
> bottom and
> at the second layer. I connect them with a lot of vias.
> 
> 
> best regards
> Bernd
> 
> 
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