[SI-LIST] Re: follow up: Re: Query about Oscillator problem

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: "Li, Tianqi . (S&T-Student)" <tlx6f@xxxxxxx>
  • Date: Sun, 31 Jan 2010 16:12:03 -0800

Li, with all due respect you are wrong.  Type 1:  NPO/C0G capacitor 
dielectric has a much lower K, lower dielectric loss, and lower ESR for 
any like size and value capacitor compared to a capacitor made from Type 
2, or Type 3 dielectric.  The typical ESR difference is in the 4:1 to 
6:1 range.  That means that in addition to the temperature stability 
they are much higher Q for the same package size / value combination.

Steve

Li, Tianqi . (S&T-Student) wrote:
> Hi Steve
>
> NO. They primarily have very different TCC. Please check the Temperature
> Coefficient plot of NPO, X7R, Y5V, via following link
> http://www.koaspeer.com/pdfs/cap8.pdf
>
> In addition, to the PLL power capacitors, what you said may be true. But
> it should be analyzed based on specific case details. Actually one of my
> former design experienced a similar temp. problem (PLL lose lock every 3
> days during temp. variation test) and I changed to NPO on PLL power pins
> and the problem never come again.
>
> Tianqi Li
>
> -----Original Message-----
> From: steve weir [mailto:weirsi@xxxxxxxxxx] 
> Sent: Sunday, January 31, 2010 5:21 PM
> To: Li, Tianqi . (S&T-Student)
> Cc: chundi srikanth; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] follow up: Re: Query about Oscillator problem
>
> Li, that is not correct.  NPO capacitors are high stability and high Q.
>
> They are great for the crystal tuning caps where both characteristics 
> are a plus.  But the high Q can actually create unwanted resonance 
> problems in the PLL power filter.
>
> Steve.
> Li, Tianqi . (S&T-Student) wrote:
>   
>> Sree,
>>
>> I forget sth. You need to check the PLL filtering capacitors of
>>     
> MCF5212.
>   
>> In most cases CPU will leave out 2 or 3 power pins for filtering PLL
>> noise. Capacitors on these pins should also use NPO for a better
>> performance.
>>
>> And you also need to find at what value of Vpp of XTAL droped to the
>>     
> PLL
>   
>> start to lose locking. If the value is out of MCF5212 spec, the root
>> cause is surely on XTAL tank circuit; If not, it might be XTAL's
>>     
> glitch
>   
>> aroused. You can use scope to test the eye diagram and find the
>>     
> glitch.
>   
>> Tianqi Li
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>>     
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>   
>> On Behalf Of Li, Tianqi . (S&T-Student)
>> Sent: Sunday, January 31, 2010 4:44 PM
>> To: chundi srikanth; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Query about Oscillator problem
>>
>> Hi Sree,
>>
>> 1) I think you should check the tuning capacitors temp. grade first.
>>     
> In
>   
>> this case you need to use NPO grade. If you are using Y5V, it won't
>>     
> work
>   
>> well when temp. changes a lot.
>>
>> 2) Make sure that the tuning capacitor's value is same as what
>> recommended in MCF5212 app. Notes.
>>
>> 3) If capacitors are OK, you need to check XTAL power consumption and
>> make sure that MCF5212 can drive the XTAL at low temp.
>>
>>
>> Tianqi Li
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>>     
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>   
>> On Behalf Of chundi srikanth
>> Sent: Saturday, January 30, 2010 10:18 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Query about Oscillator problem
>>
>> Hi Friends,
>> I have designed a board with MCF5212 Processor and it was interfaced
>>     
> to
>   
>> a
>> Pericom (saronix-ecera) NKS5 series quartz crystal. The crystals
>> operating
>> temperature was -40Deg c to 85Deg c. Earlier i tested this board and
>> everything was fine but now because the PLL was not locking and
>> processor
>> was working. So when i observed i noticed that at ambient temperature
>> the
>> crystal clock output was 2V p-p but with decrease in temperature the
>> clock
>> output was decreasing below 0.8V at -40 Deg c.
>>
>> Can you just give me an idea about this problem and what might be the
>> problem in this scenario?
>>
>> Thanks & Regards
>> Sree
>>
>>
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>   


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Steve Weir
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