[SI-LIST] extraction tool

  • From: houfei chen <hfchen73@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 14 Jul 2003 16:05:58 -0700 (PDT)

Hi, SI expert,

I read the following message from SI list and part of
it interests me a lot. I would appreciate if I could
know what extraction tools (in-house or commercial)
you are using to extract the "on-chip P/G network",
and the same question for the "166-port S-parameter
network model" for the package. Is this "on-chip P/G
network" fully represented by this "166-port S
network"? What's the "2.5 million RLC and 50k
transistor" doing here? Are they also part of the P/G

Quite a few questions coz I am interested and also
quite confused by this part. Also confusing me is that
the message is from "Scott McMorrow" whereas the
author is "Yu". That's why I can't decide the author
and direct the question to him directly.

Thanks a lot,

Msg: #14 in digest
Date: Fri, 11 Jul 2003 16:41:35 -0700
From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
Subject: [SI-LIST] [Fwd: Re: Re: Reducing SSO noise in
an FPGA]

Hi, Scott,

We have been working with a big ASIC design company on
IO-SSO problem. 
You are quite right - in order to perform an accurate
IO SSO analysis, 
we need both on-chip P/G network, and the package
data. We use our 
extraction tool to extract the on-chip P/G network,
and the package is 
166-port S-parameter network model, the whole netlist
has roughly 2.5 
million RCLs, plus 50K mosfet transistors, and the big
network - all together to simulate more than 300 I/O
SSO, and the 
shows big vdd-drop, ground bounce, and huge current
peaks. It's quite 
amazing to see all those effects, and running the
simulation just on a 
Linux desktop.



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