[SI-LIST] Re: equal length requirement for SDRAM signals
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- Date: Tue, 22 Jan 2013 18:14:11 +0100
Hi Jeff,
I think that there have been discussions in the past how accurate length
matching need to be done.
I agree totally with you, that very accurate length matching is easy to
implement for layout guys and as long it has no disadvantage it should
be done as accurate as possible.
But I have seen designs that required to increase the distance between
Controller and DRAMs in order to get the required length matching. In
addition to this the meanders have been routed so close that there was a
significant X-talk adder.
If I have a defined length mismatch i can calculate very accurate what
I'm loosing in the timing budget. But for X-talk and additional length
it is not that straight forward to estimate the effect in timing budget.
Therefore I prefer to e. g. spend 70ps in the timing budget by having
10mm length mismatch vs. an unknown impact of X-talk in my system.
One reason why we might have different experience here is, because we
are talking about different systems. I often deal e. g. with cheap DDR2
solder down systems (not terminated, low layer count, single ended DQS,
no impedance control, ... ).
I have not seen this in normal DIMM type applications on Desktop size
systems or even servers ...
Hermann
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Am 22.01.2013 16:29, schrieb Loyer, Jeff:
> Hello Herman,
> This sentence took me very much by surprise. Can you share specifics on how
> this could happen?
> "I have seen Designs being killed by over-accurate length matching"
>
> Thanks,
> Jeff Loyer
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Hermann Ruckerbauer
> Sent: Tuesday, January 22, 2013 12:58 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: equal length requirement for SDRAM signals
>
> Hello Leon,
>
> For SSO (Simultanious switching outputs) this does not help, as they will be
> aligned to the DQS anyhow.
> For the input noise on DQ this might improve situation a little bit for VDDQ
> noise, but I don't think you have so much margin that this really changes a
> lot. Of course this depends on your system speed, but usually timing margins
> are tight and you don't want to loose too much timing margin.
> On CA usually you do have a VTT plane which should not impact e. g. VDDQ too
> much from a noise point of view. So also here I expect that you loose more
> margin when doing non equal routing vs. SSN noise.
>
> ==> My expectation is, that with the small Window that you can use to
> optimize SSN you will not really gain anything from a noise point of view,
> but you will loose timing margin.
> ==> I would not recommend to do it and stay with a reasonable length matching
> accuracy.
>
> Hermann
>
> P.S. but I have seen Designs being killed by over-accurate length matching ..
> Sometimes a not so perfect matching is better than a very tight matching, but
> this depends on your system.
>
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> schrieb 李磊:
>> hi, experts,
>> in many vendors' SDRAM layout guide line, there is equal length requirement
>> for SDRAM group signals. in order to meet this, we use snake lines to reach
>> this target usually.
>> in my understanding, this kind of requirement is just only from electrical
>> timing point of view.
>> Actually from SSN point of view, different signal length should have benefit
>> on the contrary.
>> so as long as signal timing constraint is not violated, it's better to make
>> signal length unequal.
>>
>> Am I right?
>>
>> thanks.
>> BR,Leon
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