The paper is
"Simplified Design and Modeling of Surface Mount Connector Pad Transitions
for Applications at 10 to 20 Gbps NRZ", Vicich, Mcmorrow, DesignCon 2005
Let me say that the physics remain the same today. The methods I used at
that time were pretty simple. Today, we just analyze these things in high
capacity EM solvers. The biggest issue with pad stubs for edge card
connectors is the mechanical tolernace and contact wipe.
Scott McMorrow
Consultant - R&D
Teraspeed Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
On Thu, Sep 17, 2015 at 9:11 AM, jun zhang <zhangjun5960@xxxxxxxxx> wrote:
Hi Scott,
Thank you very much for offering so many suggestions. Let me digest and
consult with you again.
Hi Istvan,
Please find the paper for me. I have browsed google scholar but sadly not
find the relavant paper by Scott relavant to edge fingers.
Thank you all again
Best regards to you
Jun
On Thu, Sep 17, 2015 at 8:46 PM, Scott McMorrow <scott@xxxxxxxxxxxxx>
wrote:
Jun
THe PCIe connector was designed for rugged mechanicsl requirements.
Contact wipe is one of the critical requirements that requires a long pin
length and stub overhang
There are several strategies to reduce the effective electrical length of
the stub.
1) use lower Dk materials in the layer underneath the contact and relieve
the ground plane.
2) Increase the height from the ground plane underneath to the pad
layer. This forces more of the fields to propagate in air, thus reducing
the effective electrical length
3) If you know the mechanical tolerance dimensions of the contact landing
box, you can disconnect part of the stub end of the pad from the active
part of the pad, by placing a 5 mil cut between the two. This meeting the
contact wipe requirement and at the same time decreasing the length of the
stub
4) provide some inductive trace compensation just outside the contact pad
to counteract the capacitive effect of the stub. Unfortunately, this only
works if you can place the inductive compensation close enough.
Best regards and good question
Scott
Scott McMorrow
Consultant - R&D
Teraspeed Consulting - A Division of Samtec
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
On Thu, Sep 17, 2015 at 8:02 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
wrote:
Hi Jun,
Please note that attachments are not allowed on the SI List, the image
was stripped by the server.
Regarding your question: there were articles on this a few years back;
look up for instance Scott McMorrow's DesignCon papers...
Regards,
Istvan Novak
Oracle
On 9/17/2015 12:09 AM, jun zhang wrote:
[image: Inline image 1]edge
Hi experts,
From above figure for PCIE slot, we find that there is about 4.4mm
fingers being stubs. From my simulation from 0-10GHz, this stub issue
becomes very serious from 4-10GHz. But 4.4mm is designed for mechanical
contact purpose. Do any one knows how we can overcome its SI defect?
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best wishes,
Jun Zhang
