Goutham, I don't think "as close as possible" is a good rule of thumb for differntial pair spacing, although I don't doubt that some guidelines may actually contain this type of language. While there are advantages to very closely coupled pairs, there are also reasons for maintaining some degree of isolation. The major considerations in defining diff pair geometries are differnetial impedance and loss. You have a limited range of uncoupled impedance on a PCB, generally 40 to 65 ohms or so, so you have a similiarily limited range of differential impedance. You don't always have the luxury of closely coupled pairs if you need to acheive a fairly high differential impedance. In particular, when using devices with internal termination where you don't get to choose. You also have to consider loss in determining miminum trace widths. In the PC world I see alot of 4-5 mil trace with 6-8 mil spaced moderately coupled CMOS clocks, as well as 4-5 mil trace with 4-5 mil space tighly coupled LVDS pairs. These geometries generally yeild differential impedances between 80 and 100 ohms. I have also seen 7 mil traces with 7 mil spaces on some I/O interfaces where loss is an issue. In many cases the pair spacing is not the closest possible spacing based on DFM rules, but rather spacing is defined to acheive the desired differential impedance in combination with trace widths within the manurfacturable trace geometry window of the board, while providing an acceptable level of loss, and a reasonable degree of coupling. Its just not possible to give a rule of thumb in my opinion. Given a choice it is nice to have the overall geometry as compact as possible for routing purposes, especially for wide internal interfaces and busses, but in the case of individual I/O interfaces this is not such an issue. Hope that helps some. Brian P. Moran Signal Integrity Engineer Intel Corporation brian.p.moran@xxxxxxxxx -----Original Message----- From: Goutham.S@xxxxxxxxxx [mailto:Goutham.S@xxxxxxxxxx] Sent: Tuesday, October 09, 2001 9:18 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] differential signals spacing Hi All, In the differential trace routing (ethernet, scsi, USB etc.) , Routing guidelines mentions that the differential pairs should be routed as close as possible to effectively utilise the differential signal properties (Noise Cancellation). They don't mention the spacing in terms of mils or inches. We were earlier giving the spacing as per the PCB designer's convenience. The smallest spacing used is 5mils. As far as Manufacturering technology is concerned, spacing can be 2.5 mil and above. My doubt is that from Electrical Engineers point of view, what is the spacing requirement for differential signals. Regards Goutham Sabavat Force computers India Pvt Ltd ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu