[SI-LIST] Re: difference between transition current & peak current !!
- From: Larry Smith <LSMITH@xxxxxxxxxx>
- To: Rohit MISHRA <rohit.mishra@xxxxxx>, Kirby Goulet <kgoulet@xxxxxxxx>
- Date: Fri, 24 Jun 2011 10:53:46 -0700
For PDN analysis purposes, current is one of the most important but least
understood concepts. It is important to start from good definitions. Here are
some of the definitions that we use.
Static current: is present when the power supply is in spec but no clock is
present. This includes leakage current and current sources associated with
analog circuits (differential pair current sources, etc).
Clock edge current: comes with each clock cycle and is only present when there
is a clock. The time integral of clock edge current gives the charge consumed
by die circuits during each clock cycle. The peak instantaneous current for a
logic core may be in the 100's of amps immediately after the clock edge but it
dwindles to zero at the end of the clock period (otherwise you would not meet
timing). Clock edge current has extremely high di/dt but fortunately this is
supplied by the on-die decoupling capacitance and greatly filtered so that very
little of it makes it out of the die, through the package and onto the PCB.
Dynamic current: the time averaged clock edge current, which is the charge
consumed by the clock edge current divided by the clock period. This current
is proportional to clock frequency; if you double the frequency, you double the
dynamic current. Dynamic current is likely to be 10's of amps when the peak
instantaneous clock edge current is in the 100's of amps.
Maximum current: The maximum current consumed by the PDN as seen by the VRM or
bench power supply when the die circuits are all functioning in their "most
activity" mode. This is often the same as dynamic current under maximum use
conditions. Note that the VRM or bench power supply time constant is in mSec
to possibly uSec so this is the time average of many clock cycles.
Minimum current: VRM or bench power supply current when the die is in minimum
activity mode. The clock may be turned off or the supply may be opened by a
pass gate.
Transient current: changes in dynamic current due to power management, software
code or data handling requirements. This occurs when die circuits begin or end
the processing of packets, logic computations or memory activity. The
transient current is the difference between maximum current and minimum current
(di) and may be expressed as a percentage of maximum current. It often occurs
in just a few clock cycles (dt). If the clock is never turned off, the
transient current is likely to be near 50%. With clock gating there may be 90%
transients and power gating can produce nearly 100% transients. Intimate
knowledge of circuit operations in the system environment is required to fully
evaluate transient current.
Transient current is often a difficult and misunderstood concept. Robust PDN
design begins with an estimation of the target impedance, a primary component
of which is the transient current. Hopefully the above definitions will
clarify what transient current is in the context of PDN design. More
information can be found in our last two DesignCon papers under
http://si-list.net/files/published/ldsmith/ldsmith_papers.html
Best Regards,
Larry
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rohit MISHRA
Sent: Friday, June 24, 2011 5:24 AM
To: Kirby Goulet
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: difference between transition current & peak current !!
Most of the chip manufacturers doesn't provide transition current information
in specs instead they provide worst case peak current and quiescent current
information But to calculate pdn voltage drop it's transition current which is
all required so as a thumb rule, it's advised to use 1/2 X worst peak current
for pdn voltage drop calculation.
-----Original Message-----
From: Kirby Goulet [mailto:kgoulet@xxxxxxxx]
Sent: Friday, June 24, 2011 5:42 PM
To: Rohit MISHRA
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: difference between transition current & peak current
!!
I have not seen the terminology before, but one could be a reference to
surge currents on power-up. The limiting factor is to prevent damage from
thermal effects. The other (transition?) current could be the current step
when changing a CPU from hibernate to active - in this case maintaining the
voltage is important.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rohit MISHRA
Sent: June-24-11 7:51 AM
To: Rajan Hansa; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: difference between transition current & peak current
!!
Rajan,
Here's my 2 cents :
Peak current : It has dc as well as ac transition current. It could be
mostly dc and very little transition current or it could be very low
quiescent(dc) and mostly transition current. Actual ratio depends on
functionality of device.
Transition current : It is the switching current which device consumes
during switching, it's basically above or below to the dc(quiescent) value.
Example : If device is taking 5 ma in quiescent state and 2 ma transition
current during switching. Then peak current = 7 ma and transition current is
only 2 ma.
Rgds,
Rohit
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rajan Hansa
Sent: Friday, June 24, 2011 4:45 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] difference between transition current & peak current !!
Guys,
While calculating pdn network drop, it's generally advised to consider worst
case transition current rather than worst case peak current. I have a
problem understanding difference between worst case transition & peak
current ?
Is peak current a dc peak current while transition is ac switching current
??
Rgds,
Rajan
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