[SI-LIST] Re: decoupling capacitor placement/route
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Gene Glick" <gglick@xxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Mar 2010 15:01:38 -0700
Gene,
There are many good books on this subject. Eric Bogatin's comes to mind.
Istvan Novak's is another. Mind does as well!
In order to design a good power delivery system, it is necessary to couple
the power and ground planes together with a very thin insulator (2 mils is
a good choice.) When you do this, the location of the capacitors is
unimportant as they are all "close" to the parts they are expected to
supply. You are correct, the right thing to do is minimize the inductance
in series with these capacitors (their connecting structures). The best
you can do is connect both ends of your capacitors into their respective
planes with the lowest inductance mounting structures you can design that
are manufacturable. Don't worry about sharing pins with the ICs.
Yes, applications notes call out all sorts of bizarre methods of mounting
capacitors. Some EMI gurus do as well! Most of them are pretty unreliable
when it comes to designing your power delivery subsystem. Get one of these
books and get some good advice on how to do this design task.
Hope this helps.
Lee Ritchey
> [Original Message]
> From: Gene Glick <gglick@xxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> Date: 3/30/2010 3:04:23 PM
> Subject: [SI-LIST] decoupling capacitor placement/route
>
> Where is it best to place decoupling caps (surface mount)?
>
> 1) A trace connects an IC power pin to the cap. Then, the cap connects
> to a trace and finally a via to power plane. (these cheezy ascii
> drawings don't alway work, but here goes)
>
> |PowerPin|------| CAP |----|via|
>
>
> 2) Power pin, to short trace, to via to power plane. Then either place
> the decoupling cap top or bottom of the bard
>
> |PowerPin|-----|via|----|CAP|
>
>
>
> I contend that one reason for going to surface mount chips is to
> minimize lead inductance. Option 1 seems to negate that philosophy.
> Seems that option 2 is better in this regard. Yet, many data sheets
> recommend option 1, thinking the chip is forced to get power from the
> cap first, by nature of the physical layout. I'm willing to bet the
> inductance of the via is far lower than the trace inductance of option 1.
>
> In your experiences, which is more correct? Or maybe another method is
> better yet :)
>
> regards,
>
> gene
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