[SI-LIST] Re: ddr3 vref margin test
- From: Mustafa Özgür TUTUM <mustafa.tutum@xxxxxxxxxxxxx>
- To: <hermann.ruckerbauer@xxxxxxxxxxxxx>
- Date: Thu, 27 May 2010 17:42:48 +0300
Hello Hermann,
3Dmark is running during the test and I am changing the VrefCa and Vref DQ
externally.
Thanks.
Regards
Mustafa
From: Hermann Ruckerbauer [mailto:hermann.ruckerbauer@xxxxxxxxxxxxx]
Sent: Thursday, May 27, 2010 5:00 PM
To: Mustafa Özgür TUTUM
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] ddr3 vref margin test
Hello Mustafa,
I have also seen some tests passing independent of the Vref. I guess you
checked e. g. by introducing some Single fails e. g. by trying to isolate one
pin during runtime ?
VREF DQ and VREF CA are seperated on the SO-DMMs. Do you talk about Vref CA or
VREF DQ ?
One reason i have seen is a Memory test that is not really efficient in doing
interface testing (e. g. running in the cache most of the time, ..).
Which test are you using ?
Regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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schrieb Mustafa Özgür TUTUM:
Hi,
We are designing intel pine m platform notebooks with ddr3 support. When I have
performing voltage margin test, I have noticed that DDR3 Vref value can be
between 0 and 1.5V. In our previous designs with DDR2, voltage levels were
between 0.3-0.5V at low side and 1.1-1.4V at high sideand margins were 0.5-1.2.
I couldnot comment these results for ddr3? Can you help me? What is the wrong?
Thanks.
Best Regards
Mustafa
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