[SI-LIST] Re: ddr2-ringing and non monotonous conditions
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: kbmanick@xxxxxxxxx
- Date: Tue, 18 Jun 2013 08:53:24 +0200
Hello Balamanikandan,
Are you talking about DQ or CA bus, solder down or DIMM based ?
On both you can try to tweek the length matching to shift any non
montonics into regions where you don't care.
On DQ you can also optimize ODT configuration settings for different Ranks.
On CA you can add serial terminations and move you VTT termination to
another place (also on DQ if reall required).
for Clock you might have a chance to utlize additional clock drivers on
your controller and implement a different topology
Also with drive strenght settings you might ave a chance to reduce
ringings ..
These are the usual suspects and with some simulations you should be
able to figure out a working configuration ..
Best regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Balamanikandan K:
> Hi,
> *In DDr2 simulations, How to reduce ringing and non monotonous conditions
> when we have a point to multipoint topology and unequal loads?*
>
> * *
>
> *Please suggest me some good ideas to overcome.*
>
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