[SI-LIST] Re: ddr2 timing simulation

  • From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
  • To: <Cortex.Chen@xxxxxxxxxxxx>, <moshef@xxxxxxxxxxx>
  • Date: Tue, 5 Sep 2006 19:15:54 -0400

As Cortex says, for DDR, clock frequency equals simulation Nyquist frequency
equals data, strobe, and mask frequency. Address and control is half clock
frequency.

For non-DDR, clock is twice data and address Nyquist frequency.

The problem is that there is terminology in data sheets and advertizing
where a 667 MHz rate DDR is actually running at 333.5MHz clock rate. They
should be referring to 667Mbits per second rate for the memory.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Cortex.Chen@xxxxxxxxxxxx
Sent: Thursday, August 31, 2006 9:28 PM
To: moshef@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ddr2 timing simulation


Moshe,

CLK/DQS/DQ: 333MHz (double edge)

Address: 167MHz (1T) or 83.5MHz (2T)
(Actually value, please check the module's SPD)

Control: 167MHz(1T)

Regards,

Cortex

On 8/31/06, Moshe Frid <moshef@xxxxxxxxxxx> wrote:
>
> Can someone help me with that:
>
>
> I need to run eye pattern simulation on a 2-dimm ddr2-667 connected to
> controller
>
> In what frequency should I run the simulation at the following groups?
>
>
>
>                     1.  DQ
>
>                     2.  DQS
>
>                     3.  CLK
>
>                     4.  ADRESS
>
>                     5.  CONTROL
>
> Thanks
>
>
>
>
>
>
>
> Moshe
>
>
>
>
>
>
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