[SI-LIST] Re: ddr2 timing simulation
- From: <Cortex.Chen@xxxxxxxxxxxx>
- To: <moshef@xxxxxxxxxxx>
- Date: Fri, 1 Sep 2006 09:27:56 +0800
Moshe,
CLK/DQS/DQ: 333MHz (double edge)
Address: 167MHz (1T) or 83.5MHz (2T)
(Actually value, please check the module's SPD)
Control: 167MHz(1T)
Regards,
Cortex
On 8/31/06, Moshe Frid <moshef@xxxxxxxxxxx> wrote:
>
> Can someone help me with that:
>
>
> I need to run eye pattern simulation on a 2-dimm ddr2-667 connected to
> controller
>
> In what frequency should I run the simulation at the following groups?
>
>
>
> 1. DQ
>
> 2. DQS
>
> 3. CLK
>
> 4. ADRESS
>
> 5. CONTROL
>
> Thanks
>
>
>
>
>
>
>
> Moshe
>
>
>
>
>
>
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