[SI-LIST] Re: ddr2 ansoft / EMC2 paper available for download
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Chris Cheng <Chris.Cheng@xxxxxxxx>
- Date: Sat, 03 Nov 2007 21:40:40 -0700
Chris generally speaking locating the vias closer signal transitions
rather than further away better limits the amount of energy that ends up
bouncing around in the cavity. So, if for example we determined that we
wanted a mean stitch density of 4 vias / square inch, and we had a mean
signal via density of 4 or fewer vias / square inch, we can make our
lives easier by locating the stitch vias near the signal vias. That
agrees with your idea to place stitch vias close to signal transitions.
OTOH, if we have a lot higher signal transition density in some region
it does not necessarily follow that we will see substantial benefit by
trying to match those 1:1 with stitch vias. I want to make clear that
while it may seem intuitively appealing to think that a "return via"
matches or exactly compensates a signal via, in reality it does not. I
cannot emphasize strongly enough that any given stitch via just reflects
a certain amount of signal energy that makes it harder for that energy
to propagate into the lateral extents of the cavity versus along the z
axis where we would like it to go. If we really want the signal energy
to all transition through the z axis and out to the horizontal plane on
the new layer, it takes multiple "return" vias per signal with the right
geometry including anti-pads.
As far as injecting high speed signal energy into power cavities goes, I
agree the attendant cost can be very and unnecessarily high,
particularly at today's edge rates. However, that is not to say that it
cannot be done successfully over limited circumstances. If I can make
something work reliably and drop PCB layers by going through a power
cavity, then I am inclined to save my clients money by doing that. If
it isn't going to work reliably, then there is no point. I think an
alternate way to express Lee's point is that he has a lot of successful
experience meeting performance requirements while employing technical
compromises that have allowed him / his customers to save complications
and money. We want quantifiable measures that apply in advance of
design so that we can make these decisions intelligently.
On your point a) I think that if you look at Bruce Archambeault's
hierarchy for signal routing, it is in good agreement with your axiom.
In essence, both of them seek to avoid pumping energy through cavities
and PDS nodes unnecessarily. Good microwave routing techniques work
because the physics supports them. The catch is in the definition of
"unnecessarily". To me it is foolish to refuse to take technically
suboptimal paths when doing so successfully offers economic advantage.
As more of our industry's growth relies on consumer oriented goods with
tough ASPs I think this point becomes increasingly important. If we
really wanted to be religious about interconnects we would ban wire
bonds. But, wire bonds aren't going away. Nor should they. Getting
back to what I liked about the Ansoft / EMC2 effort is that it
demonstrated that by using these tools we can quantify what provides
value and what does not. That translates to arming us with useful
information on how to trade performance vs cost.
On your point b) I would agree that inductance severely limits our
ability to present low impedance to any package above some value in the
10's of MHz. However, several issues not the least of which are
resonances can make it a big deal to consider and manage PCB PDN
behavior substantially beyond 100MHz. If you want to talk about
specific examples, I would prefer to do that off-line.
Best Regards,
Steve.
Chris Cheng wrote:
> I have a simpler example.
> What if the trace further from the edge of the PCB get via stitches
> right next to the trace instead of at edge. Do you think the EMI noise
> will be bigger or smaller than the case with trace closer to the edge
> but via stitch at the edge far from the trace ?
> I would bet the close via case will always win.
> I believe (if indeed the example is really signal/gnd/power/signal
> stackup) this is another classic example of what I have been saying
> "two wrongs don't make one right".
> If you start by denying the return current a direct path of return
> (i.e. one reference plane is ground and the other is power) you are
> asking for trouble and whatever remedy your through at it, be it thin
> core power/ground planes, crazy via stitches is just wasting
> your effort on a improper setup.
> Switch to ground reference plane for both and even with as small as
> one via near by will make it smaller than any thin core power planes
> or crazy via stitch you can throw at the wrong reference plane case.
> For fear of sounding like a broken record, remember the two Chris
> Cheng rules of SI:
> a) Manage your signal return
> b) Decouple your PCB power/ground up to 100MHz before hitting your
> package, manage the rest at the package and die level
> All the common SI/EMI problems start with violating my two rules. :-D
>
>
> ------------------------------------------------------------------------
> *From:* steve weir [mailto:weirsi@xxxxxxxxxx]
> *Sent:* Sat 11/3/2007 7:04 PM
> *To:* Chris Cheng
> *Cc:* si-list
> *Subject:* Re: [SI-LIST] Re: ddr2 ansoft / EMC2 paper available for
> download
>
> Chris, Jason can address the specifics of that signal path. However in
> general, it is important to note tat even a stitch via does not provide
> a direct return path between the two planes of a cavity. That is true
> whether or not the two outer planes of the cavity are the same voltage
> or not. A stitch via, even one really close to a signal via provides a
> reflection surface that redirects only some of the signal energy that
> would otherwise expand further out through the cavity.
>
> With this view it should be a little bit easier to intuit why the via
> that was further from the PCB edge excited the cavity more than the one
> near the edge even though the trace on that latter signal ran parallel
> to the edge. Being closer to stitch vias along the edge, that latter
> transition saw a strong reflection boundary nearby and less total energy
> went into the cavity laterally.
>
> Best Regards,
>
>
> Steve.
>
>
> Chris Cheng wrote:
> > Steve and Jason,
> > Thanks for sharing.
> > Let me clarify a question I have from the beginning.
> > In page 21 of the presentation, it shows the signal transition
> consist of a microstrip line switching from one reference plane on one
> side (ground) to the opposite side (power). Is this really how the
> simulation and measurement is done ?
> > i.e. the image return current is denied a direct return path between
> the top reference plane (ground) and bottom (power) ?
> > Chris
> > ________________________________
> >
> > From: si-list-bounce@xxxxxxxxxxxxx on behalf of steve weir
> > Sent: Sat 11/3/2007 12:40 PM
> > To: si-list
> > Subject: [SI-LIST] Re: ddr2 ansoft / EMC2 paper available for download
> >
> >
> >
> > To all that asked to see Jason Pritchard of EMC2 and Ansoft's joint
> > paper on via stitching and EMI it is available via anonymous ( quasi )
> > on the ipblox FTP server:
> >
> > ftp.ipblox.com
> > username: anonymous@xxxxxxxxxx
> > password: anonymous
> >
> > It is located in the ftp://ftp.ipblox.com/Ansoft_first_pass_2007/
> directory.
> >
> > regards,
> >
> >
> > Steve
> >
> > --
> > Steve Weir
> > Teraspeed Consulting Group LLC
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> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
> California office
> (408) 884-3985 Business
> (707) 780-1951 Fax
>
> Main office
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> Oregon office
> (503) 430-1065 Business
> (503) 430-1285 Fax
>
> http://www.teraspeed.com <http://www.teraspeed.com/>
> This e-mail contains proprietary and confidential intellectual
> property of Teraspeed Consulting Group LLC
> ------------------------------------------------------------------------------------------------------
> Teraspeed(R) is the registered service mark of Teraspeed Consulting
> Group LLC
>
> This email and any attachments thereto may contain private,
> confidential, and privileged material for the sole use of the intended
> recipient. Any review, copying, or distribution of this email (or any
> attachments) by others is strictly prohibited. If you are not the
> intended recipient, please contact the sender immediately and
> permanently delete the original and any copies of this email and any
> attachments thereto.
>
--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(408) 884-3985 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
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