[SI-LIST] Re: clocks,caps&hspice!

  • From: Eddy <eddyvk@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Sun, 8 Jul 2007 11:07:54 -0700 (PDT)

John,

If you are talking about a clock generator IC or a
clock oscillator module then YES, the clock output of
those is a buffer with some driving capability. They
usually have a spec to be capable of (!) driving a
certain capacitive load. I see a lot of engineers
getting confused by these spec's as if you need to add
the capacitive load as a form of termination. This is
not the case!
A common spec for a clock output would be 15pF. The
original meaning of the 15pF simply is a fan-out of 5
with an average input capacitance of 3pF. I guess this
is from the days of 2 micron CMOS. ;-)
If you need to design or test a clock driver, not
knowing where or how it will be used then you will
have to stick to the spec, load it with 15pF or
whatever spec'd and verify the properties. Of course
if you know the exact loading of the clock output then
try to model this specific load as accurate as
possible. Do not add a capacitor on a clock output
because it is spec'd to drive a certain capacitive
load.

Eddy
Fremont CA
www.phaselink.com


--- john smith <pranksteroma@xxxxxxxxx> wrote:
>
> Hi Guys,
> Is the 'clock signal' driven by a buffer?
> 
> Why do we use capacitors as loads, wont they load
> the driving ckt like
> resistors?
> 
> And in hspice does the simulator automatically
> connect an infinite resistor
> to open ends?
> 
> Thanks,
> JS



       
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