I have a simpler possible explanation: the internal termination isn't actually
enabled. Study the input circuit diagrams and double-check the register
settings. An un-terminated line will generally have a plateau in the incident
wave which can be non-monotonic. Un-terminated lines will have a positive
reflection and over terminated line a negative reflection. If adding an
external term results in a well-behaved waveform, it is possible that this is
the only termination. Also, the high loading from (2) 100 terminations in
parallel would likely cause a noticeable drop in min/max swings.
________________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on behalf of
Istvan Novak <istvan.novak@xxxxxxxxxxx>
Sent: Friday, June 17, 2016 8:32 AM
To: johnson4hw@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: clock signal non-monotonic nature
If you search the SI list archives, you can find
discussions on this subject in the past.
As others mentioned, probe loading, non-ideal
termination, etc all can contribute to this, but
the usual and most likely suspect is the reflection
from the capacitance from the device input. A
reasonable amount of load capacitance is expected
and OK at the end of the line and at the very end of
the line, where this load capacitance is, it just creates
a little rounding based on the time constant you can
calculate. Further away from the termination,
however, the reflected wave from the load capacitance,
together with reactances along the way, will have a
tendency to create a non-monotonic glitch.
Regards,
Istvan Novak
Oracle
On 6/16/2016 11:34 AM, john h wrote:
Hi SI Gurus,
I am new to hardware and I am thankful for your inputs on this .
I am probing a clock signal on the board. The clock is 125MHz differential
and I am probing it at the receiver end. The receiver is of BGA package
and I am probing at the BGA end (via )at the bottom side of the board. (
IC is placed on the Top side)
The clock pins at the receiver are terminated with 100E internally.
The clock waveform is seen to be of non-monotonic nature. A dip is seen on
the rising and falling edge approximately at 80% of signal level. At that
point during ramp , the signal dips down a bit and then rise again to 100%
of the signal level.
I could not exactly understand on the issue.
To debug further, I removed the AC caps at the receiver (thereby isolating
the receiver) and placed a parallel 100E .And I probed across the 100E.
the signal looks to be completely fine. monotonic and no dips are seen on
the edge.
I could not exactly understand on this. Is the dip seen on the first case
is due to the reflection from the receiver. but the receiver is internally
terminated as per the datasheet. Appreciate your inputs on this.
Thank you,
Johnson
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