[SI-LIST] Re: clock 48MHz simulation(one driver & two loads)
- From: Perry Qu <perry.qu@xxxxxxxxxxx>
- To: tseng.morgan@xxxxxxxxxxxx
- Date: Wed, 27 Oct 2004 12:50:47 -0400
You need to make sure that packaging of receiver is properly captured in
your simulation, especially for big BGAs. In such case, what you measured
at BGA pad is not what you see at receiver I/O in simulation.
Regards
Perry
acquking wrote:
> Hi all
>
> I do a clock 48MHz simulation(one driver & two loads) and have a
> correlation with simulation and measure result.The comparision
> performs a little time difference in rising and falling
> edge,especially falling edge.The difference is about 500ps in rising
> edge and 1ns in falling edge.(rising & falling time measue is
> between 0.8 and 2V,reciver spec is 1.2ns for maximum value).
> I think it due to spike poisition in edge is not a good match by
> simulation and measure result.IBIS is a behavior model that means
> one driver strength ability of clk generator is to one load to meet
> original design rule.Is there problem to perform 2 loads?Should V-I
> and V-t curve in this model be modified to meet 2 loads?
>
> Regards
> Morgan
>
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--
Perry Qu
Design & Qualification | 600 March Road
Alcatel Canada | Ottawa, ON K2K 2E6, Canada
DID: (613) 7846720 | FAX: (613) 5993642
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