[SI-LIST] clock 48MHz simulation(one driver & two loads)
- From: "acquking" <tseng.morgan@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 26 Oct 2004 15:18:38 -0000
Hi all
I do a clock 48MHz simulation(one driver & two loads) and have a
correlation with simulation and measure result.The comparision
performs a little time difference in rising and falling
edge,especially falling edge.The difference is about 500ps in rising
edge and 1ns in falling edge.(rising & falling time measue is
between 0.8 and 2V,reciver spec is 1.2ns for maximum value).
I think it due to spike poisition in edge is not a good match by
simulation and measure result.IBIS is a behavior model that means
one driver strength ability of clk generator is to one load to meet
original design rule.Is there problem to perform 2 loads?Should V-I
and V-t curve in this model be modified to meet 2 loads?
Regards
Morgan
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