[SI-LIST] Re: clock 2nd harmonic
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 17 May 2012 12:35:49 -0700
If the clock driver output has parasitic capacitance to both Vdd and Vss
(item 4) then one can expect it to draw current from Vdd on both edges
(item 1). This will cause a 130 MHz power noise component on Vdd w.r.t
Vss. May be more aggressive decoupling will help?
Thanks,
Vinu
On 05/17/2012 12:09 PM, Joel Brown wrote:
> I found this in a paper:
> Second Harmonic Emissions
> • Currents draw on both edges of the clock
> • Clock duty cycle different of 50% (minor factor -10%)
> • Crowbar current in clock drivers (small factor)
> • Clock driver output has nearly equal capacitance to both Vss and Vdd
> (dominant factor)
>
> Not sure what the last one means or what to do about it.
>
>
> On Thu, May 17, 2012 at 11:43 AM, Joel Brown<joel@xxxxxxxxxx> wrote:
>
>> I am having an EMI problem with the second harmonic of a 65 MHz clock.
>> There is a strong emission at 130 MHz.
>> What is most likely causing the second harmonic and how can I reduce it?
>> The clock waveform does not look seriously distorted.
>>
>> Thanks
>>
>>
>>
>>
>
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