[SI-LIST] Re: "checkered" copper plane question
- From: "Hill, Michael J" <michael.j.hill@xxxxxxxxx>
- To: <christopher.heard@xxxxxxxxxxxx>, <williamm@xxxxxxx>
- Date: Tue, 13 May 2003 11:26:40 -0700
Hi,
I have often wondered about this as well and have never heard a =
definitive explanation (lots of people seem to do it because everyone =
else does). I had always assumed it had the following benefits:
1) it reduces the amount of copper to be removed and thus decreases etch =
chemical usage
2) it evens out the etch across the board so that the etch chemicals =
don't get depleted in locations that would otherwise require a lot of =
etching. This would even out the etch time across the board so that =
small features are not over etched while waiting for the large areas to =
be removed.
3) it would provide more even thermal expansion effects between the top =
and bottom layers of the board - and reduce board bending with =
temperature because the top and bottom copper expansions would be more =
similar (than the case with lots of copper on one side and large copper =
voids on the other).
4) This one is a stretch (although I have actually used them this way)- =
it makes reworking a prototype board easier because you have dummy nodes =
you can solder parts & wires to.=20
I am a little confused about the "copper thieving" plating explanation =
as all the board processing I have been involved with required doing the =
via and plane copper plating before etch (typically this is =
electroplating, so if etch is done first, then it is not always possible =
to connect electrically to all of the surfaces to be plated). Maybe =
Chris intended etch, not plating, or maybe I'm unaware of new processing =
methods (it has been 3 or 4 years..).
As for the EM effects - these squares would have to be very carefully =
designed to have a reliable and predictable effect from an EM =
perspective, so unless they were talking it up as a special design and =
knew what they were talking about, I would doubt any EM explanation.
Mike
-----------------------
Michael Hill Ph.D.
Sr. Packaging Engineer
Intel Corporation
MS CH5-157
5000 W. Chandler Blvd
Chandler Arizona, 85226
ph: 480-552-6013
fax: 480-552-1295
-----Original Message-----
From: christopher.heard@xxxxxxxxxxxx
[mailto:christopher.heard@xxxxxxxxxxxx]
Sent: Tuesday, May 13, 2003 10:37 AM
To: williamm@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: "checkered" copper plane question
Bill,
This is called "copper thieving". The concept is that the presence of =
the
small squares will distribute the plating across the area of the pcb.
Theiving is generally used when there are areas on a pcb surface that =
have
densely packed plated features mixed with very little plated features.
Connectors that have many holes in a small area on a pcb may have =
theiving
squares added around the connector pattern to control the amount of =
plating
in the holes.
Chris
**********************
Chris Heard
Teradyne
Work: 603-879-1031
Cell: 508-277-5780
SMS Text Message: 5082775780@xxxxxxxxx
Email: christopher.heard@xxxxxxxxxxxx
=
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"Bill Mueller" =
=20
<williamm@xxxxxxx To: =
<si-list@xxxxxxxxxxxxx> =
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> cc: =
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Sent by: Subject: [SI-LIST] =
"checkered" copper plane question =20
si-list-bounce@fr =
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eelists.org =
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05/13/2003 01:36 =
=20
PM =
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Please respond to =
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williamm =
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Hello all,
I've been hitting a couple embedded design shows lately
and have been seeing a couple prototype boards that have
the top and bottom copper planes 'checkered'
That is instead of a large continuous plane, the plane has
been cut into a grid of 1-2mm squares.
Has anyone else seen this? What are the benifits of this
type of layout?
Thanks,
-Bill
BTW: The guys manning the booth had answers
ranging from 'I don't know' to 'better aestetics' to 'complex
proprietary EMI interfusion grid' :)
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