[SI-LIST] Re: capacitor impedance in time domain
- From: Doug Brooks <doug@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Jan 2005 16:34:02 -0800
Assuming we are looking at a model like this
driver >txline>cap>gnd
You can look at this from the two boundary conditions first. With a "large"
value cap, this looks like a shorted line. The first thing that happens is
there is a large negative reflection and then the line stabilizes with zero
voltage at the far end. Then the cap charges based on the RC time constant
between the output impedance of the driver and the value of the cap.
With a "small" cap, the cap charges quickly, it looks like an open line,
there is a 100% positive reflection, and the voltage at the far end of the
line rises to the open ended driver voltage.
With a cap value "in between," these two effects will combine, based on the
relative values. Exactly what happens depends on the values chosen for the
driver output impedance, the Zo of the line, and the cap value.
This can be modeled pretty easily with a tool like Hyperlynx.
Doug Brooks
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