[SI-LIST] Re: asymmetrical stack-ups

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 20 Jun 2013 13:22:49 -0700

The generic guidelines are to maintain channel continuity end-to-end as 
much as possible.  To do that well you need to understand your transmit 
and receive silicon as it is packaged.  Where you are going to 
transition return path:

Transition the signals with the least HF energy and least susceptibility 
to cross-talk and timing disturbances.
Transition the fewest number of times possible.

More separation reduces cross-talk.  The places to push copper close 
together is between power and ground, and between signal and return.  
The limitation on signal to return is etch width and etch tolerance to 
maintain a given impedance.  The places to push copper apart are signals 
to signals.

Steve.


On 6/20/2013 11:10 AM, train stop wrote:
> What are the general guidelines regarding implementing asymetrical
> stack-ups to compensate for a GND-Sig-Sig-PWR in order to encourage
> coupling to the utility layers for return current paths?  Are there
> recommendations to the thickness of the dielectric thickness between the
> Sig-Sig layer versus the GND-SIG or SIG-PWR.....so for interfaces below
> 400Mhz would an acceptable guideline be x3's.......I am just looking for
> some guidelines given lack of access to modeling tools.
>
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