[SI-LIST] Re: anlog and digital power plane isolation with ferrite bead good idea?

  • From: "Cheng, Chris" <chris.cheng@xxxxxx>
  • To: steve weir <weirsi@xxxxxxxxxx>
  • Date: Sat, 8 Jan 2011 02:39:41 +0000

I have been jumping up and down in every PCIe conferences I attended asking the 
reasons behind the trade off between jitter transfer (which has been spec and 
documented) and accumulation (which has been totally ignored).
I am shocked that some top committee members just simply brush aside the jitter 
accumulation issue or totally ignorant about it.
At the end of the day, the closest explanation I got was at the beginning some 
people wanted to save a few cents on the oscillator and choose to use a sh*tty 
clock source that has lots of jitter. The only way to get around it is by 
tracking the jitter and drop the PLL bandwidth. That makes as much sense as 
"pick your favorite inner-city" crime rate is too high, let's open up the jail 
house and let every criminal out on the street. Since everyone in the street is 
now a criminal, happy happy... Clean up your clock source and lock up all the 
offending PLL noise source along the way.
I would like the same people who push for the jitter transfer presentations do 
the same thing on jitter accumulation. Let's see at the end of the day which is 
more important.
Once we accept jitter accumulation is important and re-optimize the PLL against 
it, I believe the power filter design will be much more simple and manageable.
Cheers,

Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company

+1 510 413 5977 / Tel
chris.cheng@xxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA





-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Thursday, January 06, 2011 6:05 PM
To: Cheng, Chris
Cc: Alexandre Desnoyers; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: anlog and digital power plane isolation with ferrite 
bead good idea?

Chris, I agree that given known PLL characteristics an appropriate power
source is straightforward design work.  The fact is that we have these
standards like PCIe that set the PLL bandwidth well below 10MHz which
means it is possible to accumulate a lot of VCO error due to PLL power
noise before the control loop can correct it.  There are various
approaches the chip designer can use to deal with this problem all of
which I am sure you are aware.  The poor guy designing the PCB gets
stuck with whatever the chip design imposes.  What infuriates me is that
chip vendors do not disclose the parameters they require, instead
insisting on cookbook designs that are only half-cooked.

Best Regards,


Steve
Cheng, Chris wrote:
> There is nothing exotic about the PLL filter optimization and 
> characterization if you understand the fundamentals of the PLL design.
> I tested and wrote the first app note on PLL in that server company and 
> worked with the analog designers on the first voltage regulators for their 
> PLLs.
> I have two theories for the lag of information available :
>
> a) Even for a well designed PLL with loop bandwidth optimized to prevent 
> jitter accumulation, you will still find frequencies where you can knock the 
> PLL out of spec with as low as a few mV simply because of the high gain VCO. 
> The ferrite bead can in theory damp the noise down to those level but no one 
> can guarantee the substrate noise will not exceed that limit. Once you 
> publish those low noise tolerance and if your customer can somehow 
> demonstrate somewhere in the entire chip he/she can pick up those mV's of 
> noise, you have a huge liability to deal with. The best course of action is 
> to push for the bead to guarantee damping at that point below normal noise 
> budget (your typical +/-5% noise in general chip spec) and hide the real 
> noise number and get it over with.
>
> b) There are so many SerDes designs with obsession in jitter transfer such 
> that the loop bandwidth is so low that you have a broadband jitter 
> accumulation problem. The range you have to protect against power noise is so 
> wide that a simple LC/bead and C filter will be hard if not impossible to 
> design. I suspect you can find a range of frequencies where even after 
> applying the filters and with the theoretical noise limit will still be able 
> to knock the PLL out of spec. This is the time when a lot of designer/vendor 
> will choose to look the other way and simply hide or not publish such 
> problem. I am not saying this happen in every PLL design, but certainly I 
> have seen evidence of them especially for those who set their bandwidth in 
> the few MHz range.
>
> I have said many times in this forum, you can't have it both ways. You either 
> pick jitter transfer or accumulation as your demon. I have chosen mine, 
> what's yours ?
>
> Chris Cheng
> Distinguished Technologist , Electrical
> Hewlett-Packard Company
>
> +1 510 413 5977 / Tel
> chris.cheng@xxxxxx / Email
> 4209 Technology Dr
> Fremont, CA 94538
> USA
>
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of Alexandre Desnoyers
> Sent: Thursday, January 06, 2011 2:05 AM
> To: steve weir; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: anlog and digital power plane isolation with ferrite 
> bead good idea?
>
>  Hello Steve,
> I've been following this thread with much interest.
>
> I just have a problem with doing my homework:  it's almost impossible when
> ICvendors do not want to provide a minimum of information.  I requested some
> very specific information from the two biggest "PC compatible processor" IC
> vendors, and both of them answered to use the reference design ferrite
> filters ONLY, and they didn't provide the information I requested to
> actuallydo my homework.
>
> Maybe you have some tips to share with us, apart from making a test board or
> changing vendor.
>
>
> I had a private discussion with Istvan Novak about PLL supply noise
> sensitivity characterization, and he was telling me that it was not trivial
> for Sun/Oracle ASIC staff to simulate.  He also tried himself to
> characterizeone IC by measurement, and found it very difficult.
>
> I would like to suggest that the "brains" of our industry get together and
> publish a test scheme that would provide us the required information.   I'm
> sure that some IC vendors have such test in-house, but I haven't seen any
> publications (IEEE or other) describing such test setup in details.
>
>
> With the proliferation of high-speed serial link, it seems that the IC
> vendors recommend one bead filter for each interface. So for a typical
> processor with SATA, Ethernet, PCIe and USB3, each of these interface
> "requires" an independent filter.  I would like to see a SPICE simulation
> showing the interaction between each of these supplies with all the
> parasiticelements, maybe then I would be convinced to use one filter for
> each.
>
>
>
> Looking forward to hear your presentation at DesignCon.  Hopefully there
> willbe representative from the major IC manufacturers in the room....
>
>
> Regards,
>
> Alexandre Desnoyers
> Electronic Design Engineer
> Qtechnology A/S
> Valby Langgade 142, 1.sal - 2500 Valby - Denmark - www.qtec.com[1]
>
>
> P.S.  If I had followed the recommended filtering, my 3"x4" board would have
> had 19 ferrite-bead filters for only 3 ICs.....
>
>
>
>
> steve weir wrote: Dong, the key is that either someone does the homework or
> there can be no guarantee that the design will work over the expected
> operating conditions. Steve. Dong Kim wrote: Thanks everyone for the answers
> and opinions. >From reading all the responses, I see two distinct camps of
> opinions. Of course, if I get all the right parameters, files and the tools
> to simulate, I will have better psudo-facts to present. Most of my recent
> board designs, I did not have split power planes between analog and digital
> and found no problem. May be because the board sizes are large (22"x19.5")
> and 26 layers+ which includes multiple power and ground planer caps in the
> stackup. What I am designing is a half size add-on card with FPGA with
> multiple serdes, DDR2 memories, and other memories. I guess I will let my
> PDNguy make the decision to use the ferrite since I do not see any clear
> answer. I will post the result when the board is fabed and all tested out.
> Happy New Year, Dong KIm, --- On Tue, 1/4/11, steve weir
> <weirsi@xxxxxxxxxx>[2]wrote: From: steve weir <weirsi@xxxxxxxxxx>[3]
> Subject:[SI-LIST] Re: anlog and digital power plane isolation with ferrite
> bead good idea? To: "Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx>[4] Cc:
> "Cheng, Chris" <chris.cheng@xxxxxx>[5], "Tom Dagostino"
> <tom@xxxxxxxxxxxxx>[6], "Joel Brown" <joel@xxxxxxxxxx>[7], "Dan Smith"
> <Dan.Smith@xxxxxxxxx>[8], "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>[9], "Dong
> Kim" <kimdongsik_us@xxxxxxxxx>[10], si-list@xxxxxxxxxxxxx[11], "Istvan
> Novak"<istvan.novak@xxxxxxx>[12], "liuluping 41830"
> <liuluping@xxxxxxxxxx>[13]Date: Tuesday, January 4, 2011, 6:59 PM Stefan
> theyare narrow etch segments that form small inductors. Steve. Stefan Milnor
> wrote: What is a "trench and draw bridge" - in circuit design ?
> -----OriginalMessage----- From: si-list-bounce@xxxxxxxxxxxxx[14]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[15]] On Behalf Of Cheng, Chris Sent:
> Tuesday, January 04, 2011 4:09 PM To: Tom Dagostino; 'Joel Brown'; 'Dan
> Smith'; 'steve weir' Cc: 'Lee Ritchey'; 'Dong Kim';
> si-list@xxxxxxxxxxxxx[16]; 'Istvan Novak'; 'liuluping 41830' Subject:
> [SI-LIST] Re: anlog and digital power plane isolation with ferrite bead good
> idea? First off I have to apologize for tangenting off from the original
> discussion which is isolating digital and analog power planes with beads.
> Personally I don't believe in them for most of the situations and at most
> something like a trench and a draw bridge will probably work. But too many
> discussions about applying beads in PLL filtering followed and I think we
> need to clarify a few points. There always two opposite sides of PLL loop
> bandwidth trade off, jitter transfer vs. jitter accumulation. If you come
> from the current SerDes designers, you will most likely believe in jitter
> transfer and cut your loop bandwidth to as low as you can do. If you come
> from the classic PLL applications such as CPU or ASIC internal clocks, you
> will most likely be more concern about core noise and jitter accumulation. I
> happened to come from the later school so a natural thing to do is to push
> the loop bandwidth of the PLL to as high as possible without sacrificing
> phase margin too much. The beauty of it is the PLL then can self correct its
> jitter up to near the PLL loop bandwidth. The side effect of this is you can
> easily build an internal regulator with modest damping and pretty much clean
> up the jitter from low to all the way to near the loop bandwidth frequency.
> This is when the external power filtering become interesting. Because the
> frequency needing protection is relatively high, the ferrite bead is ideal
> for the application because it has high loss at those high frequency. That
> would also allows a relatively small capacitor to form the filter tree and
> itmakes a great compact external filter. The ESR of the bead can be spec to
> relatively low to avoid the DC drop but I found sometimes I need a small
> series resistor just to keep the Q low enough. That was the original design
> when we first investigate this PLL jitter accumulation effects in the late
> 80's and published the app notes for our then ASIC vendors. If you come from
> the "fear everything from the source jitter transfer so let's drop bandwidth
> as low as we can" camp, well, then why are you worry about jitter
> accumulation and build the power filter trees in the first place ? That's
> like breaking your right leg and then complain about why can't you run......
> But that's a debate we have to wait for the next time. Happy New Year, Chris
> Cheng Distinguished Technologist , Electrical Hewlett-Packard Company +1 510
> 413 5977 / Tel chris.cheng@xxxxxx[17] / Email 4209 Technology Dr Fremont, CA
> 94538 USA -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx[18]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[19]] On Behalf Of Tom Dagostino Sent:
> Monday, January 03, 2011 10:11 PM To: 'Joel Brown'; 'Dan Smith'; 'steve
> weir'Cc: 'Lee Ritchey'; 'Dong Kim'; si-list@xxxxxxxxxxxxx[20]; 'Istvan
> Novak'; 'liuluping 41830' Subject: [SI-LIST] Re: anlog and digital power
> plane isolation with ferrite bead good idea? I find the "follow the
> referencedesign" approach very iffy at best. Any filter that is places
> between the "outside world" and the PLL or whatever only reduces the noise
> from the outside world by XdB(f). So if the noise the IC vendor had in the
> reference design was only 50 mV and your outside world is at 100 mV or has a
> different frequency content you may have an issue. You need specs for what
> the chip can tolerate, not a cook book design. Tom Dagostino Teraspeed Labs
> 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@xxxxxxxxxxxxx[21]
> www.teraspeed.com[22] Teraspeed Consulting Group LLC 121 North River Drive
> Narragansett, RI 02882 401-284-1827 www.teraspeed.com[23] -----Original
> Message----- From: si-list-bounce@xxxxxxxxxxxxx[24]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[25]] On Behalf Of Joel Brown Sent:
> Monday, January 03, 2011 7:09 PM To: 'Dan Smith'; 'steve weir' Cc: 'Lee
> Ritchey'; 'Dong Kim'; si-list@xxxxxxxxxxxxx[26]; 'Istvan Novak'; 'liuluping
> 41830' Subject: [SI-LIST] Re: anlog and digital power plane isolation with
> ferrite bead good idea? I encounter this very frequently when it comes to
> designing with parts that have separate analog and/or PLL power rails. It is
> very common for manufacturers of these parts to recommend either in a
> datasheet, application note or reference design to use a ferrite bead which
> in theory could reduce the noise that is present on the digital power
> supplies. Sometimes a manufacturers P/N is given for the ferrite bead and
> sometimes no information is given. For me when dealing with a vendor a
> typical scenario would be like this: Submit a question to mysupport.com
> "whatare the noise and ripple requirement of the analog and PLL power
> inputs"Answer one week later "Just follow the reference design, we have
> tested it and it works. If you don't follow it then good luck". My options
> are as follows: Do a PDN analysis of the whole board and determine if the
> noise is low enough to directly connect the analog and/or PLL to the digital
> power. In reality this is a guesstimate because you can with some serious
> work determine with some degree of accuracy the PDN impedance but no IC
> manufacturer will tell you the input power current vs frequency
> characteristics of their part which is what you need to know what the noise
> voltage will actually be. Do an analysis of the ferrite / capacitor network
> to see how it behaves and look for problems like resonances. Replace or
> supplement the ferrite bead with a linear regulator to further reduce the
> noise. This only works for certain frequencies that the regulator will
> rejectinput noise. In the end whatever I choose to do, I think making noise
> measurements on the actual circuit is probably the most useful piece of
> information. If I didn't get it right then I can tweak the ferrite or
> capacitors to get it working. This hasn't happened yet. Its too bad that the
> manufacturers of ICs can't come up with some standardized way specifying
> current and noise on power pins. Everybody has IBIS or SPICE models of the
> signal I/O pins but when it comes to power it's a black hole. Joel
> -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx[27]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[28]] On Behalf Of Dan Smith Sent:
> Monday, January 03, 2011 1:34 PM To: steve weir Cc: Lee Ritchey; Dong Kim;
> si-list@xxxxxxxxxxxxx[29]; Istvan Novak; liuluping 41830 Subject: [SI-LIST]
> Re: anlog and digital power plane isolation with ferrite bead good idea?
> Steve that is a good point. Dong, in my experience the most difficult piece
> of the design (of late, all my designs) is getting the requirements out of
> the vendors. I use a common spreadsheet that I customize for each chip
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