Stefan they are narrow etch segments that form small inductors. Steve. Stefan Milnor wrote: > What is a "trench and draw bridge" - in circuit design ? > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of Cheng, Chris > Sent: Tuesday, January 04, 2011 4:09 PM > To: Tom Dagostino; 'Joel Brown'; 'Dan Smith'; 'steve weir' > Cc: 'Lee Ritchey'; 'Dong Kim'; si-list@xxxxxxxxxxxxx; 'Istvan Novak'; > 'liuluping 41830' > Subject: [SI-LIST] Re: anlog and digital power plane isolation with > ferrite bead good idea? > > First off I have to apologize for tangenting off from the original > discussion which is isolating digital and analog power planes with > beads. Personally I don't believe in them for most of the situations and > at most something like a trench and a draw bridge will probably work. > But too many discussions about applying beads in PLL filtering followed > and I think we need to clarify a few points. > There always two opposite sides of PLL loop bandwidth trade off, jitter > transfer vs. jitter accumulation. > If you come from the current SerDes designers, you will most likely > believe in jitter transfer and cut your loop bandwidth to as low as you > can do. > If you come from the classic PLL applications such as CPU or ASIC > internal clocks, you will most likely be more concern about core noise > and jitter accumulation. > I happened to come from the later school so a natural thing to do is to > push the loop bandwidth of the PLL to as high as possible without > sacrificing phase margin too much. The beauty of it is the PLL then can > self correct its jitter up to near the PLL loop bandwidth. The side > effect of this is you can easily build an internal regulator with modest > damping and pretty much clean up the jitter from low to all the way to > near the loop bandwidth frequency. This is when the external power > filtering become interesting. Because the frequency needing protection > is relatively high, the ferrite bead is ideal for the application > because it has high loss at those high frequency. That would also allows > a relatively small capacitor to form the filter tree and it makes a > great compact external filter. The ESR of the bead can be spec to > relatively low to avoid the DC drop but I found sometimes I need a small > series resistor just to keep the Q low enough. That was the original > design when we > > first investigate this PLL jitter accumulation effects in the late 80's > and published the app notes for our then ASIC vendors. > If you come from the "fear everything from the source jitter transfer so > let's drop bandwidth as low as we can" camp, well, then why are you > worry about jitter accumulation and build the power filter trees in the > first place ? That's like breaking your right leg and then complain > about why can't you run...... > But that's a debate we have to wait for the next time. > > Happy New Year, > > Chris Cheng > Distinguished Technologist , Electrical > Hewlett-Packard Company > > +1 510 413 5977 / Tel > chris.cheng@xxxxxx / Email > 4209 Technology Dr > Fremont, CA 94538 > USA > > > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of Tom Dagostino > Sent: Monday, January 03, 2011 10:11 PM > To: 'Joel Brown'; 'Dan Smith'; 'steve weir' > Cc: 'Lee Ritchey'; 'Dong Kim'; si-list@xxxxxxxxxxxxx; 'Istvan Novak'; > 'liuluping 41830' > Subject: [SI-LIST] Re: anlog and digital power plane isolation with > ferrite bead good idea? > > I find the "follow the reference design" approach very iffy at best. > Any > filter that is places between the "outside world" and the PLL or > whatever > only reduces the noise from the outside world by XdB(f). So if the > noise > the IC vendor had in the reference design was only 50 mV and your > outside > world is at 100 mV or has a different frequency content you may have an > issue. You need specs for what the chip can tolerate, not a cook book > design. > > Tom Dagostino > Teraspeed Labs > 13610 SW Harness Lane > Beaverton, OR 97008 > 503-430-1065 > tom@xxxxxxxxxxxxx > www.teraspeed.com > > Teraspeed Consulting Group LLC > 121 North River Drive > Narragansett, RI 02882 > 401-284-1827 > www.teraspeed.com > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On > Behalf Of Joel Brown > Sent: Monday, January 03, 2011 7:09 PM > To: 'Dan Smith'; 'steve weir' > Cc: 'Lee Ritchey'; 'Dong Kim'; si-list@xxxxxxxxxxxxx; 'Istvan Novak'; > 'liuluping 41830' > Subject: [SI-LIST] Re: anlog and digital power plane isolation with > ferrite > bead good idea? > > I encounter this very frequently when it comes to designing with parts > that > have separate analog and/or PLL power rails. It is very common for > manufacturers of these parts to recommend either in a datasheet, > application > note or reference design to use a ferrite bead which in theory could > reduce > the noise that is present on the digital power supplies. Sometimes a > manufacturers P/N is given for the ferrite bead and sometimes no > information > is given. For me when dealing with a vendor a typical scenario would be > like > this: > > Submit a question to mysupport.com "what are the noise and ripple > requirement of the analog and PLL power inputs" > > Answer one week later "Just follow the reference design, we have tested > it > and it works. If you don't follow it then good luck". > > My options are as follows: > > Do a PDN analysis of the whole board and determine if the noise is low > enough to directly connect the analog and/or PLL to the digital power. > In reality this is a guesstimate because you can with some serious work > determine with some degree of accuracy the PDN impedance but no IC > manufacturer will tell you the input power current vs frequency > characteristics of their part which is what you need to know what the > noise > voltage will actually be. > > Do an analysis of the ferrite / capacitor network to see how it behaves > and > look for problems like resonances. > > Replace or supplement the ferrite bead with a linear regulator to > further > reduce the noise. This only works for certain frequencies that the > regulator > will reject input noise. > > In the end whatever I choose to do, I think making noise measurements on > the > actual circuit is probably the most useful piece of information. If I > didn't > get it right then I can tweak the ferrite or capacitors to get it > working. > This hasn't happened yet. > > Its too bad that the manufacturers of ICs can't come up with some > standardized way specifying current and noise on power pins. Everybody > has > IBIS or SPICE models of the signal I/O pins but when it comes to power > it's > a black hole. > > Joel > > > > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On > Behalf Of Dan Smith > Sent: Monday, January 03, 2011 1:34 PM > To: steve weir > Cc: Lee Ritchey; Dong Kim; si-list@xxxxxxxxxxxxx; Istvan Novak; > liuluping > 41830 > Subject: [SI-LIST] Re: anlog and digital power plane isolation with > ferrite > bead good idea? > > Steve that is a good point. Dong, in my experience the most difficult > piece > of the design (of late, all my designs) is getting the requirements out > of > the vendors. I use a common spreadsheet that I customize for each chip. > I > then ask the vendor to fill in all the blanks for me and those blanks > are > P/S ripple requirements over which frequencies that their chips is > guaranteed to work. With that, you have the requirements feeding into > your > PDS design as Steve mentions. In one case I did have to meet a 0.5% > ripple > requirement (yeah, not a typo although I didn't believe it) so I did add > one > RC filter to a low current pin. But that has only been once in the last > 5 > designs I did. > > I am empathetic with you because the vendor climb as described above is > very > steep (and for me, I still haven't reached the top... :-) ). At this > point > I would say slightly better than half of the vendors now give me this > information. > > Regards, > > Dan > > -----Original Message----- > From: steve weir [mailto:weirsi@xxxxxxxxxx] > Sent: Monday, January 03, 2011 1:08 PM > To: Dan Smith > Cc: Lee Ritchey; Dong Kim; si-list@xxxxxxxxxxxxx; Istvan Novak; > liuluping > 41830 > Subject: Re: [SI-LIST] Re: anlog and digital power plane isolation with > ferrite bead good idea? > > Dan, ferrite beads are way too often used where they are not needed, and > are way too often applied without proper consideration to managing their > side-effects. This frequently gets people into trouble, and likely > contributed to the failure you experienced. > > The problem Dong presents includes lack of: requirements specification, > design information, and expertise on the part of Dong. Dong's > misgivings may well be justified. However, if Dong goes ahead and > designs a PDN without working against a set of requirements, if he is > successful it will only be by happenstance. That neither vindicates, > nor refutes his colleague's design. > > If Dong's colleague has done his homework, then Dong's colleague can > show Dong that: > > 1. The design meets a stated set of requirements obtained either from > vendor specifications, and/or measurements. > 2. The use of ferrite beads made it easier to meet those requirements. > > The places where ferrite beads make sense are very distinct. Usually, > no more than casual inspection of PDN requirements immediately indicate > whether a ferrite bead based filter is worth considering. Assuming that > Dong's colleague did his homework, it should be very easy for him to > point Dong at the requirements that led to use of a ferrite bead and to > challenge Dong to find a better alternate solution. If on the other > hand, the PDN engineer has simply followed a cookbook recipe then > whether the design works or not depends on how well that recipe > encompasses the variables such as: component placement, stack-up, and > other loads on the same power rail(s) in the implementation. > > Steve. > > Dan Smith wrote: > >> Dong, >> >> The best way to convince him, perhaps, is to ignore his advice and do >> > a > proper PDS design like you want to. Then, when the results come in > prove it > to him based on your evidence. I have been doing 3GIG and 10GIG SERDES > designs for 8 years and only used ferrite beads once. That was my first > SERDES design and I too followed advice of someone else - It was also > the > only time my SERDES design didn't work! Since, I have never used a > ferrite > bead (initially ignoring several people and doing my own engineering) > and > have been successful for the last 7 years - including across backplanes. > The key, though, is performing a PDS (which includes instantaneous > currents > and a stable power supply) and not just simply removing the ferrite > beads. > >> Dan >> >> -----Original Message----- >> From: si-list-bounce@xxxxxxxxxxxxx >> > [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of Lee Ritchey > >> Sent: Monday, January 03, 2011 9:44 AM >> To: Dong Kim; steve weir; si-list@xxxxxxxxxxxxx >> Cc: Istvan Novak; liuluping 41830 >> Subject: [SI-LIST] Re: anlog and digital power plane isolation with >> > ferrite bead good idea? > >> Dong, >> I have attached a PDS design program from Altera. Notice that it does >> > not > >> include any ferrite beads. same kind of thing is available from >> > Xilinx. > >> Yes, old applications notes from both Altera an Xilinx said to use >> > ferrite > >> beads. This was never good advice and has finally been taken from >> > their > app > >> notes, but not before may engineers got conned into using ferrite >> > beads. > >> Lee >> >> -------------------------------------------------- >> From: "Dong Kim" <kimdongsik_us@xxxxxxxxx> >> Sent: Monday, December 27, 2010 4:03 PM >> To: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>; "steve weir" >> <weirsi@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx> >> Cc: "Istvan Novak" <istvan.novak@xxxxxxx>; "liuluping 41830" >> <liuluping@xxxxxxxxxx> >> Subject: [SI-LIST] anlog and digital power plane isolation with >> > ferrite > bead > >> good idea? >> >> >> >>> Hi, >>> >>> My colleague, a PDN engineer, insist he has to use ferrite bead to >>> > isolate > >>> an analog power plane from digital plane for an large FPGA I am using >>> > on > a > >>> PCB design. >>> I have been trying to convince him it would be better to have good >>> decoupling filter by adding inner-plane capacitance and decoupling >>> > caps. > >>> But, he is insisting I should prove it either by theory or simulation >>> before he can change his mind to remove the isolation ferrite bid and >>> > add > >>> planer cap in my board stack-up. I could not really prove by >>> > methodical > >>> thory nor have time and tool to simulate. >>> >>> With my shallow knowledge, it will just end with arguing even if he >>> > agree > >>> to do what I tell him to do. >>> My knowledge is from my past board design with similar >>> > characteristics, > I > >>> did not use the ferrite to isolate the analog and digital power >>> > planes. > >>> It worked fine. >>> I also has shown him Lee Ritch's 2nd volume of "Right the first >>> > time". > >>> But, I guess it did not convince him. >>> >>> Please someone explain why analog and digital power isolation by >>> > using > may > >>> be not a good idea. >>> >>> Please help. >>> >>> Thanks, >>> >>> Dong S. Kim >>> >>> >>> >>> ------------------------------------------------------------------ >>> To unsubscribe from si-list: >>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >>> >>> or to administer your membership from a web page, go to: >>> //www.freelists.org/webpage/si-list >>> >>> For help: >>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >>> >>> >>> List technical documents are available at: >>> http://www.si-list.net >>> >>> List archives are viewable at: >>> //www.freelists.org/archives/si-list >>> >>> Old (prior to June 6, 2001) list archives are viewable at: >>> http://www.qsl.net/wb6tpu >>> >>> >>> >>> >> ------------------------------------------------------------------ >> To unsubscribe from si-list: >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >> >> or to administer your membership from a web page, go to: >> //www.freelists.org/webpage/si-list >> >> For help: >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >> >> >> List technical documents are available at: >> http://www.si-list.net >> >> List archives are viewable at: >> //www.freelists.org/archives/si-list >> >> Old (prior to June 6, 2001) list archives are viewable at: >> http://www.qsl.net/wb6tpu >> >> >> >> >> > > > -- > Steve Weir > IPBLOX, LLC > 150 N. Center St. #211 > Reno, NV 89501 > www.ipblox.com > > (775) 299-4236 Business > (866) 675-4630 Toll-free > (707) 780-1951 Fax > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > > -- Steve Weir IPBLOX, LLC 150 N. Center St. #211 Reno, NV 89501 www.ipblox.com (775) 299-4236 Business (866) 675-4630 Toll-free (707) 780-1951 Fax ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu