[SI-LIST] Re: anlog and digital power plane isolation with ferrite bead good idea?
- From: Doug Smith <doug@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 03 Jan 2011 23:02:16 -0800
Hi Joel and the group,
Something to watch out for regarding measurements. If you know what
waveshape to expect, say a clock waveform, then problems with the
measurement will be obvious. But with power supply noise, you may not
know what it looks like on the scope (if you are making time domain
measurements). The problem is that there are common measurement problems
that can add 50% or more to the peak to peak amplitude of power ripple
at some frequencies. Generally it happens in the upper octave of the
bandwidth of many probes. Only (active) probes with damping resistors on
the tip are relatively immune to this effect. Some active differential
and single ended probes have a lot of overshoot with just the inductance
of the smallest tip that comes with the probe, especially if the probe
design is older than six years or so. I have seen problems with both
probe resonance (above) and probe pickup of noise that is not actually
on the signal being measured but rather elsewhere in the circuit or even
the room.
Doug
On 1/3/11 7:08 PM, Joel Brown wrote:
> I encounter this very frequently when it comes to designing with parts that
> have separate analog and/or PLL power rails. It is very common for
> manufacturers of these parts to recommend either in a datasheet, application
> note or reference design to use a ferrite bead which in theory could reduce
> the noise that is present on the digital power supplies. Sometimes a
> manufacturers P/N is given for the ferrite bead and sometimes no information
> is given. For me when dealing with a vendor a typical scenario would be like
> this:
>
> Submit a question to mysupport.com "what are the noise and ripple
> requirement of the analog and PLL power inputs"
>
> Answer one week later "Just follow the reference design, we have tested it
> and it works. If you don't follow it then good luck".
>
> My options are as follows:
>
> Do a PDN analysis of the whole board and determine if the noise is low
> enough to directly connect the analog and/or PLL to the digital power.
> In reality this is a guesstimate because you can with some serious work
> determine with some degree of accuracy the PDN impedance but no IC
> manufacturer will tell you the input power current vs frequency
> characteristics of their part which is what you need to know what the noise
> voltage will actually be.
>
> Do an analysis of the ferrite / capacitor network to see how it behaves and
> look for problems like resonances.
>
> Replace or supplement the ferrite bead with a linear regulator to further
> reduce the noise. This only works for certain frequencies that the regulator
> will reject input noise.
>
> In the end whatever I choose to do, I think making noise measurements on the
> actual circuit is probably the most useful piece of information. If I didn't
> get it right then I can tweak the ferrite or capacitors to get it working.
> This hasn't happened yet.
>
> Its too bad that the manufacturers of ICs can't come up with some
> standardized way specifying current and noise on power pins. Everybody has
> IBIS or SPICE models of the signal I/O pins but when it comes to power it's
> a black hole.
>
> Joel
>
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Dan Smith
> Sent: Monday, January 03, 2011 1:34 PM
> To: steve weir
> Cc: Lee Ritchey; Dong Kim; si-list@xxxxxxxxxxxxx; Istvan Novak; liuluping
> 41830
> Subject: [SI-LIST] Re: anlog and digital power plane isolation with ferrite
> bead good idea?
>
> Steve that is a good point. Dong, in my experience the most difficult piece
> of the design (of late, all my designs) is getting the requirements out of
> the vendors. I use a common spreadsheet that I customize for each chip. I
> then ask the vendor to fill in all the blanks for me and those blanks are
> P/S ripple requirements over which frequencies that their chips is
> guaranteed to work. With that, you have the requirements feeding into your
> PDS design as Steve mentions. In one case I did have to meet a 0.5% ripple
> requirement (yeah, not a typo although I didn't believe it) so I did add one
> RC filter to a low current pin. But that has only been once in the last 5
> designs I did.
>
> I am empathetic with you because the vendor climb as described above is very
> steep (and for me, I still haven't reached the top... :-) ). At this point
> I would say slightly better than half of the vendors now give me this
> information.
>
> Regards,
>
> Dan
>
> -----Original Message-----
> From: steve weir [mailto:weirsi@xxxxxxxxxx]
> Sent: Monday, January 03, 2011 1:08 PM
> To: Dan Smith
> Cc: Lee Ritchey; Dong Kim; si-list@xxxxxxxxxxxxx; Istvan Novak; liuluping
> 41830
> Subject: Re: [SI-LIST] Re: anlog and digital power plane isolation with
> ferrite bead good idea?
>
> Dan, ferrite beads are way too often used where they are not needed, and
> are way too often applied without proper consideration to managing their
> side-effects. This frequently gets people into trouble, and likely
> contributed to the failure you experienced.
>
> The problem Dong presents includes lack of: requirements specification,
> design information, and expertise on the part of Dong. Dong's
> misgivings may well be justified. However, if Dong goes ahead and
> designs a PDN without working against a set of requirements, if he is
> successful it will only be by happenstance. That neither vindicates,
> nor refutes his colleague's design.
>
> If Dong's colleague has done his homework, then Dong's colleague can
> show Dong that:
>
> 1. The design meets a stated set of requirements obtained either from
> vendor specifications, and/or measurements.
> 2. The use of ferrite beads made it easier to meet those requirements.
>
> The places where ferrite beads make sense are very distinct. Usually,
> no more than casual inspection of PDN requirements immediately indicate
> whether a ferrite bead based filter is worth considering. Assuming that
> Dong's colleague did his homework, it should be very easy for him to
> point Dong at the requirements that led to use of a ferrite bead and to
> challenge Dong to find a better alternate solution. If on the other
> hand, the PDN engineer has simply followed a cookbook recipe then
> whether the design works or not depends on how well that recipe
> encompasses the variables such as: component placement, stack-up, and
> other loads on the same power rail(s) in the implementation.
>
> Steve.
>
> Dan Smith wrote:
>> Dong,
>>
>> The best way to convince him, perhaps, is to ignore his advice and do a
> proper PDS design like you want to. Then, when the results come in prove it
> to him based on your evidence. I have been doing 3GIG and 10GIG SERDES
> designs for 8 years and only used ferrite beads once. That was my first
> SERDES design and I too followed advice of someone else - It was also the
> only time my SERDES design didn't work! Since, I have never used a ferrite
> bead (initially ignoring several people and doing my own engineering) and
> have been successful for the last 7 years - including across backplanes.
> The key, though, is performing a PDS (which includes instantaneous currents
> and a stable power supply) and not just simply removing the ferrite beads.
>> Dan
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee Ritchey
>> Sent: Monday, January 03, 2011 9:44 AM
>> To: Dong Kim; steve weir; si-list@xxxxxxxxxxxxx
>> Cc: Istvan Novak; liuluping 41830
>> Subject: [SI-LIST] Re: anlog and digital power plane isolation with
> ferrite bead good idea?
>> Dong,
>> I have attached a PDS design program from Altera. Notice that it does not
>> include any ferrite beads. same kind of thing is available from Xilinx.
>>
>> Yes, old applications notes from both Altera an Xilinx said to use ferrite
>> beads. This was never good advice and has finally been taken from their
> app
>> notes, but not before may engineers got conned into using ferrite beads.
>>
>> Lee
>>
>> --------------------------------------------------
>> From: "Dong Kim"<kimdongsik_us@xxxxxxxxx>
>> Sent: Monday, December 27, 2010 4:03 PM
>> To: "Lee Ritchey"<leeritchey@xxxxxxxxxxxxx>; "steve weir"
>> <weirsi@xxxxxxxxxx>;<si-list@xxxxxxxxxxxxx>
>> Cc: "Istvan Novak"<istvan.novak@xxxxxxx>; "liuluping 41830"
>> <liuluping@xxxxxxxxxx>
>> Subject: [SI-LIST] anlog and digital power plane isolation with ferrite
> bead
>> good idea?
>>
>>
>>> Hi,
>>>
>>> My colleague, a PDN engineer, insist he has to use ferrite bead to
> isolate
>>> an analog power plane from digital plane for an large FPGA I am using on
> a
>>> PCB design.
>>> I have been trying to convince him it would be better to have good
>>> decoupling filter by adding inner-plane capacitance and decoupling caps.
>>>
>>> But, he is insisting I should prove it either by theory or simulation
>>> before he can change his mind to remove the isolation ferrite bid and add
>>> planer cap in my board stack-up. I could not really prove by methodical
>>> thory nor have time and tool to simulate.
>>>
>>> With my shallow knowledge, it will just end with arguing even if he
> agree
>>> to do what I tell him to do.
>>> My knowledge is from my past board design with similar characteristics,
> I
>>> did not use the ferrite to isolate the analog and digital power planes.
>>> It worked fine.
>>> I also has shown him Lee Ritch's 2nd volume of "Right the first time".
>>> But, I guess it did not convince him.
>>>
>>> Please someone explain why analog and digital power isolation by using
> may
>>> be not a good idea.
>>>
>>> Please help.
>>>
>>> Thanks,
>>>
>>> Dong S. Kim
>>>
>>>
>>>
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>
> --
> Steve Weir
> IPBLOX, LLC
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