[SI-LIST] Re: adjacent power plane spacing with sensitive power nodes
- From: Ignas Mikulevicius <mikulevi@xxxxxxxxx>
- To: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Mon, 12 Oct 2009 10:23:21 -0700
Thank you for the explanations, Istvan and Scott,
It makes sense, I'm surprised now that I haven't ever considered that up til
this point. Better late than never I guess. Is there any way to
quantitatively measure this effect? We probed the PLL and VCC supply pins
for the PCIe transceivers with a high speed scope on the FPGA vias on the
solder side of the board and were only seeing 40-50mv of peak-to-peak noise
on the 1.2V and 1.0V supplies, which would seem to be acceptable, given the
specification calls for +/- 5%. Is this a meaningful measurement? Perhaps it
is not accurately reflecting what the actual device is seeing?
On another note, if these PLL supply nodes were next to a ground plane
instead of a power plane, would we not be concerned with the same effect,
i.e. transient noise on the ground plane coupling into the node?
Ignas
On Mon, Oct 12, 2009 at 10:16 AM, Scott McMorrow <scott@xxxxxxxxxxxxx>wrote:
> That would be 2 plates form one capacitor, not two
>
>
>
> Scott McMorrow wrote:
>
> Ignas,
> The coupling mechanism is capacitive. Two parallel adjacent plates form
> two very nice high quality capacitors.
>
> Scott
>
>
> Ignas Mikulevicius wrote:
>
>
> Thanks for the advice, Scott. Pardon my ignorance but could you
> explain how the power plane noise from one layer couples into adjacent
> layer power planes? I can fathom how a high speed signal with a fast
> edge and significant voltage swing would couple into a power plane on
> an adjacent layer. But I would think that a steady +12V or +3.3V power
> plane that has been properly filtered and is fed from the output of
> the voltage regulator, and with all the consuming devices bypassed and
> decoupled, would not have enough noise energy to significantly impact
> power islands on adjacent layers. For this reason I have always
> treated power planes as potential victims to crosstalk effects, and
> never as aggressors. I would greatly appreciate some insight on this.
> Thank you!
>
> On Fri, Oct 9, 2009 at 3:13 PM, Scott McMorrow <scott@xxxxxxxxxxxxx
> <mailto:scott@xxxxxxxxxxxxx> <scott@xxxxxxxxxxxxx>> wrote:
>
> Yes. I'd suggest a quick turn fabrication of a board with an
> additional layers to ground reference the power fills and isolate
> them from each other.
>
>
>
> Ignas Mikulevicius wrote:
>
> Hello,
> First, some background:
> I have a PCB design that is experiencing some jitter issues
> that we are
> trying to get to the bottom of. It is a PCI Express design
> utilizing a
> Xilinx FPGA. The PCI Express transceivers are powered by 1.0V core
> circuitry, and 1.2V circuitry for the actual transmitter and
> the PLL. The
> core and the PLL circuitry are extremely sensitive to noise.
> One theory brought up was that we might be getting noise
> coupled into these
> sensitive nodes from adjacent power planes. The nodes are
> implemented as
> mini-planes on various layers of a 12 layer PCB.
> For example, one of the PLL mini islands is on layer 8, with a
> +12V plane on
> layer 7, with only a 3.4 mil spacing between the planes. There
> is no
> adjacent ground plane, only a signal plane on layer 9, which
> is 12 mils
> away. Similarly, layer 12 contains the 1.0V core mini-island
> as well as the
> 1.2V transmitter power supply mini-plane. Layer 11 is flooded
> with +3.3V,
> with a 2.9 mil separation from layer 12.
>
> *My question: Is it possible that noise on the +12V and +3.3V
> planes is
> coupling into the sensitive transceiver nodes and causing jitter?*
>
> My initial opinion was that any ripple on the voltage planes
> would be too
> small to actually couple into an adjacent plane, but maybe I
> am wrong? I
> have read some of the archived posts considering similar
> topics, but did not
> seem to find a definitive response.
> Thank you very much in advance,
> Ignas M.
>
>
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> Scott McMorrow
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> --
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
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