[SI-LIST] Re: adjacent power plane spacing with sensitive power nodes
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Ignas Mikulevicius <mikulevi@xxxxxxxxx>
- Date: Mon, 12 Oct 2009 12:48:50 -0400
Hi Ignas,
If you measure the 12V plane and find that it is sufficiently quiet,
then of course there is no problem
with strong coupling to other rails. However, keep in mind that
'sufficiently quiet' means different
things on a 12V rail and a PLL supply rail. On a 12V rail hundreds of
mV noise is usually not an
issue (just from the point of view of the 12V rail functioning
properly), but just a few mV noise
on a PLL supply could be a disaster. So we have to ask ourselves: does
it make sense to bypass
the 12V rail so heavily that its noise is acceptable even for PLLs?
Technically we could do that,
but it may not be economical.
In this context the highest risk comes from the high-frequency burst
noise of DC-DC converters
getting out to the 12V rail. It is in the hundreds of MHz frequency
range today, and with vertically
aligned power planes the coupling in that frequency range can be very
strong.
Regards,
Istvan Novak
SUN Microsystems
Ignas Mikulevicius wrote:
> Thanks for the advice, Scott. Pardon my ignorance but could you explain how
> the power plane noise from one layer couples into adjacent layer power
> planes? I can fathom how a high speed signal with a fast edge and
> significant voltage swing would couple into a power plane on an adjacent
> layer. But I would think that a steady +12V or +3.3V power plane that has
> been properly filtered and is fed from the output of the voltage regulator,
> and with all the consuming devices bypassed and decoupled, would not have
> enough noise energy to significantly impact power islands on adjacent
> layers. For this reason I have always treated power planes as potential
> victims to crosstalk effects, and never as aggressors. I would greatly
> appreciate some insight on this.
> Thank you!
> On Fri, Oct 9, 2009 at 3:13 PM, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
>
>
>> Yes. I'd suggest a quick turn fabrication of a board with an additional
>> layers to ground reference the power fills and isolate them from each other.
>>
>>
>>
>> Ignas Mikulevicius wrote:
>>
>>
>>> Hello,
>>> First, some background:
>>> I have a PCB design that is experiencing some jitter issues that we are
>>> trying to get to the bottom of. It is a PCI Express design utilizing a
>>> Xilinx FPGA. The PCI Express transceivers are powered by 1.0V core
>>> circuitry, and 1.2V circuitry for the actual transmitter and the PLL. The
>>> core and the PLL circuitry are extremely sensitive to noise.
>>> One theory brought up was that we might be getting noise coupled into
>>> these
>>> sensitive nodes from adjacent power planes. The nodes are implemented as
>>> mini-planes on various layers of a 12 layer PCB.
>>> For example, one of the PLL mini islands is on layer 8, with a +12V plane
>>> on
>>> layer 7, with only a 3.4 mil spacing between the planes. There is no
>>> adjacent ground plane, only a signal plane on layer 9, which is 12 mils
>>> away. Similarly, layer 12 contains the 1.0V core mini-island as well as
>>> the
>>> 1.2V transmitter power supply mini-plane. Layer 11 is flooded with +3.3V,
>>> with a 2.9 mil separation from layer 12.
>>>
>>> *My question: Is it possible that noise on the +12V and +3.3V planes is
>>> coupling into the sensitive transceiver nodes and causing jitter?*
>>>
>>> My initial opinion was that any ripple on the voltage planes would be too
>>> small to actually couple into an adjacent plane, but maybe I am wrong? I
>>> have read some of the archived posts considering similar topics, but did
>>> not
>>> seem to find a definitive response.
>>> Thank you very much in advance,
>>> Ignas M.
>>>
>>>
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>> --
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882
>> (401) 284-1827 Business
>> (401) 284-1840 Fax
>>
>> http://www.teraspeed.com
>>
>> Teraspeed® is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
>>
>>
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